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Change subject: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
......................................................................
Patch Set 3: Code-Review+1
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Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58811 )
Change subject: Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods"
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> which CL would give ~12ms savings Maulik ?
Hi Subrata,
This is base CL which would allow us to make s0ix functional.
Once we disable dynamic GPIO PM from devicetree, it'll enable us to give 12ms savings.
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Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Meera Ravindranath, Angel Pons, Nick Vaccaro, Patrick Rudolph.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Angel Pons, Nick Vaccaro, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods"
......................................................................
Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods"
This reverts commit 1399442289607acc5203fb12df64e9081b3c3aa4.
Reason for revert:
Some Cr50 chips with old firmware version (x.y.22) don't support
long pulse interrupt command, requiring dynamic GPIO PM to be disabled
to intercept short pulse interrupt.
Due to this coreboot needs to expose SGPM, RGPM and EGPM ACPI methods
to support power gating of GPIO communities from the kernel when dynamic
GPIO PM is disabled.
BUG=b:204832081
BRANCH=None
Test= S0ix works with dynamic PM disabled.
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Change-Id: I2b5b00878062f8a499641d7a47db54ed078cd6cf
---
M src/soc/intel/alderlake/acpi/gpio.asl
1 file changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/58811/4
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Change subject: mb/google,intel: Split chromeos.c files
......................................................................
mb/google,intel: Split chromeos.c files
Move all the low-level GPIO support in bootmode.c files and build
them for all stages. Keep ChromeOS related ACPI and lbtable support
in chromeos.c files and build them only for ramstage.
Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/google/auron/Makefile.inc
A src/mainboard/google/auron/bootmode.c
M src/mainboard/google/auron/chromeos.c
M src/mainboard/google/beltino/Makefile.inc
A src/mainboard/google/beltino/bootmode.c
M src/mainboard/google/beltino/chromeos.c
M src/mainboard/google/butterfly/Makefile.inc
A src/mainboard/google/butterfly/bootmode.c
M src/mainboard/google/butterfly/chromeos.c
M src/mainboard/google/jecht/Makefile.inc
A src/mainboard/google/jecht/bootmode.c
M src/mainboard/google/jecht/chromeos.c
M src/mainboard/google/link/Makefile.inc
A src/mainboard/google/link/bootmode.c
M src/mainboard/google/link/chromeos.c
M src/mainboard/google/parrot/Makefile.inc
A src/mainboard/google/parrot/bootmode.c
M src/mainboard/google/parrot/chromeos.c
M src/mainboard/google/slippy/Makefile.inc
A src/mainboard/google/slippy/bootmode.c
M src/mainboard/google/slippy/chromeos.c
M src/mainboard/google/stout/Makefile.inc
A src/mainboard/google/stout/bootmode.c
M src/mainboard/google/stout/chromeos.c
M src/mainboard/intel/baskingridge/Makefile.inc
A src/mainboard/intel/baskingridge/bootmode.c
M src/mainboard/intel/baskingridge/chromeos.c
M src/mainboard/intel/emeraldlake2/Makefile.inc
A src/mainboard/intel/emeraldlake2/bootmode.c
M src/mainboard/intel/emeraldlake2/chromeos.c
M src/mainboard/intel/strago/Makefile.inc
A src/mainboard/intel/strago/bootmode.c
M src/mainboard/intel/strago/chromeos.c
M src/mainboard/samsung/lumpy/Makefile.inc
A src/mainboard/samsung/lumpy/bootmode.c
M src/mainboard/samsung/lumpy/chromeos.c
M src/mainboard/samsung/stumpy/Makefile.inc
A src/mainboard/samsung/stumpy/bootmode.c
M src/mainboard/samsung/stumpy/chromeos.c
39 files changed, 346 insertions(+), 277 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/59011/4
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Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Angel Pons, Subrata Banik, Nick Vaccaro, Patrick Rudolph.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Angel Pons, Subrata Banik, Nick Vaccaro, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods"
......................................................................
Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods"
This reverts commit 1399442289607acc5203fb12df64e9081b3c3aa4.
Reason for revert:
Some Cr50 chips with old firmware version (x.y.22) don't support
long pulse interrupt command, requiring dynamic GPIO PM to be disabled
to intercept short pulse interrupt.
Due to this coreboot needs to expose SGPM, RGPM and EGPM ACPI methods
to support power gating of GPIO communities from the kernel when dynamic
GPIO PM is disabled.
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Change-Id: I2b5b00878062f8a499641d7a47db54ed078cd6cf
---
M src/soc/intel/alderlake/acpi/gpio.asl
1 file changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/58811/3
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