coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google,intel: Split chromeos.c files
by build bot (Jenkins) (Code Review) 08 Nov '21

08 Nov '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59011 ) Change subject: mb/google,intel: Split chromeos.c files ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/stout/bootmode.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132585): https://review.coreboot.org/c/coreboot/+/59011/comment/2d2f8fb3_ba2f2505 PS5, Line 44: printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n", space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/59011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Gerrit-Change-Number: 59011 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 08 Nov 2021 15:28:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55367 to look at the new patch set (#50). Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... soc/intel/elkhartlake: Introduce Intel PSE The Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization. The PSE hosts new functions, including remote out-of-band device management, network proxy, embedded controller lite and sensor hub. This CL enables the user to provide the base address of the PSE FW blob which will then be loaded by the FSP-S onto the ARM controller. PSE FW will do the initialization work of PSE controller and it's peripherals. The loading of PSE FW should have negligible impact on boot time unless PSE controller could not locate PSE FW and FSP will attempt to redo PSE FW loading and wait for PSE handshake until it times out. Once PSE controller locate PSE FW, it will do initialization concurrently by itself with coreboot booting. It also adds PSE related FSP-S UPD settings which enables the setup of peripheral ownership (assigned to the PSE or x86 subsystem) and interrupts. These assignments need to take place at a given point in the boot process and cannot be changed later. To verify if PSE FW is loaded properly, the user could enable PchPseShellEnabled flag and the log will be printed at PSE UART 2. For further info please refer to doc #611825 (for HW overview) and #614110 (for PSE EDS). Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/elkhartlake/romstage/fsp_params.c 5 files changed, 169 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/55367/50 -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 50 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/amd/majolica:FMAP Increase EC FW space to 148KB for Type-C adaptor
by Bao Zheng (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Zheng Bao, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59010 to look at the new patch set (#2). Change subject: mb/amd/majolica:FMAP Increase EC FW space to 148KB for Type-C adaptor ...................................................................... mb/amd/majolica:FMAP Increase EC FW space to 148KB for Type-C adaptor The next 20kByte after 128k of stock BIOS is optional to enable the type-C DC adaptor. If you use the 148kByte, don't forget to fill the 0x20000-0x21000 which is ROMSIG to all FFs or 0s. The old EC_majolica.bin can still be used without building error and problems, except the type-C DC adaptor can not be used. The commands which gets the new 148kByte EC_majolica.bin $> dd if=BIOS.bin of=1.bin bs=4k count=32 $> printf '\xff%.0s' {1..4096} > 2.bin $> dd if=BIOS.bin of=3.bin bs=4k skip=33 count=4 $> cat 1.bin 2.bin 3.bin > EC_majolica.bin Change-Id: Ib311e46c8765f17a1af5bc0b00c387268f4cfae5 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/majolica/Kconfig M src/mainboard/amd/majolica/board.fmd M src/mainboard/amd/majolica/chromeos.fmd 3 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/59010/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib311e46c8765f17a1af5bc0b00c387268f4cfae5 Gerrit-Change-Number: 59010 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] mb/google,intel: Split chromeos.c files
by Kyösti Mälkki (Code Review) 08 Nov '21

08 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59018 ) Change subject: [WIP] mb/google,intel: Split chromeos.c files ...................................................................... [WIP] mb/google,intel: Split chromeos.c files Move all the low-level GPIO support in bootmode.c files and build them for all stages. Keep ChromeOS related ACPI and lbtable support in chromeos.c files and build them only for ramstage. Change-Id: Ib4ccd31edc5ab6c4bc7890a8de1ae270141d18a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/bootmode.c M src/mainboard/google/asurada/chromeos.c M src/mainboard/google/brya/Makefile.inc A src/mainboard/google/brya/bootmode.c M src/mainboard/google/brya/chromeos.c M src/mainboard/google/cherry/Makefile.inc A src/mainboard/google/cherry/bootmode.c M src/mainboard/google/cherry/chromeos.c M src/mainboard/google/corsola/Makefile.inc R src/mainboard/google/corsola/bootmode.c M src/mainboard/google/daisy/Makefile.inc A src/mainboard/google/daisy/bootmode.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/dedede/Makefile.inc A src/mainboard/google/dedede/bootmode.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/eve/Makefile.inc A src/mainboard/google/eve/bootmode.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/Makefile.inc A src/mainboard/google/fizz/bootmode.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/foster/Makefile.inc A src/mainboard/google/foster/bootmode.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gale/Makefile.inc A src/mainboard/google/gale/bootmode.c M src/mainboard/google/gale/chromeos.c M src/mainboard/google/glados/Makefile.inc A src/mainboard/google/glados/bootmode.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/gru/Makefile.inc A src/mainboard/google/gru/bootmode.c M src/mainboard/google/gru/chromeos.c M src/mainboard/google/hatch/Makefile.inc A src/mainboard/google/hatch/bootmode.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/kahlee/Makefile.inc A src/mainboard/google/kahlee/bootmode.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/kukui/Makefile.inc A src/mainboard/google/kukui/bootmode.c M src/mainboard/google/kukui/chromeos.c M src/mainboard/google/nyan/Makefile.inc A src/mainboard/google/nyan/bootmode.c M src/mainboard/google/nyan/chromeos.c M src/mainboard/google/nyan_big/Makefile.inc A src/mainboard/google/nyan_big/bootmode.c M src/mainboard/google/nyan_big/chromeos.c M src/mainboard/google/nyan_blaze/Makefile.inc A src/mainboard/google/nyan_blaze/bootmode.c M src/mainboard/google/nyan_blaze/chromeos.c M src/mainboard/google/oak/Makefile.inc A src/mainboard/google/oak/bootmode.c M src/mainboard/google/oak/chromeos.c M src/mainboard/google/octopus/Makefile.inc A src/mainboard/google/octopus/bootmode.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/peach_pit/Makefile.inc A src/mainboard/google/peach_pit/bootmode.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/poppy/Makefile.inc A src/mainboard/google/poppy/bootmode.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/rambi/Makefile.inc A src/mainboard/google/rambi/bootmode.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/Makefile.inc A src/mainboard/google/reef/bootmode.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/smaug/Makefile.inc A src/mainboard/google/smaug/bootmode.c M src/mainboard/google/smaug/chromeos.c M src/mainboard/google/storm/Makefile.inc A src/mainboard/google/storm/bootmode.c M src/mainboard/google/storm/chromeos.c M src/mainboard/google/trogdor/Makefile.inc A src/mainboard/google/trogdor/bootmode.c M src/mainboard/google/trogdor/chromeos.c M src/mainboard/google/veyron/Makefile.inc A src/mainboard/google/veyron/bootmode.c M src/mainboard/google/veyron/chromeos.c M src/mainboard/google/veyron_mickey/Makefile.inc A src/mainboard/google/veyron_mickey/bootmode.c M src/mainboard/google/veyron_mickey/chromeos.c M src/mainboard/google/veyron_rialto/Makefile.inc A src/mainboard/google/veyron_rialto/bootmode.c M src/mainboard/google/veyron_rialto/chromeos.c M src/mainboard/google/volteer/Makefile.inc A src/mainboard/google/volteer/bootmode.c M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/zork/Makefile.inc A src/mainboard/google/zork/bootmode.c M src/mainboard/google/zork/chromeos.c M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/bootmode.c M src/mainboard/intel/adlrvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/Makefile.inc A src/mainboard/intel/coffeelake_rvp/bootmode.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/glkrvp/Makefile.inc A src/mainboard/intel/glkrvp/bootmode.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/icelake_rvp/Makefile.inc A src/mainboard/intel/icelake_rvp/bootmode.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/Makefile.inc A src/mainboard/intel/jasperlake_rvp/bootmode.c M src/mainboard/intel/jasperlake_rvp/chromeos.c M src/mainboard/intel/kblrvp/Makefile.inc A src/mainboard/intel/kblrvp/bootmode.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/Makefile.inc A src/mainboard/intel/kunimitsu/bootmode.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/shadowmountain/Makefile.inc A src/mainboard/intel/shadowmountain/bootmode.c M src/mainboard/intel/shadowmountain/chromeos.c M src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/bootmode.c M src/mainboard/intel/tglrvp/chromeos.c M src/mainboard/intel/wtm2/Makefile.inc A src/mainboard/intel/wtm2/bootmode.c M src/mainboard/intel/wtm2/chromeos.c 125 files changed, 1,023 insertions(+), 849 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/59018/1 diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index 601b485..de7421b 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -2,22 +2,20 @@ bootblock-y += memlayout.ld bootblock-y += bootblock.c -bootblock-y += chromeos.c verstage-y += memlayout.ld -verstage-y += chromeos.c verstage-y += reset.c romstage-y += memlayout.ld romstage-y += boardid.c -romstage-y += chromeos.c romstage-y += regulator.c romstage-y += romstage.c romstage-y += sdram_configs.c +all-y += bootmode.c ramstage-y += memlayout.ld ramstage-y += boardid.c -ramstage-y += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c ramstage-y += regulator.c diff --git a/src/mainboard/google/asurada/bootmode.c b/src/mainboard/google/asurada/bootmode.c new file mode 100644 index 0000000..b3ccc4e --- /dev/null +++ b/src/mainboard/google/asurada/bootmode.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> +#include <security/tpm/tis.h> + +#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_EC_AP_INT); + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_H1_AP_INT); + gpio_input_pullup(GPIO_SD_CD); + gpio_output(GPIO_RESET, 0); + gpio_output(GPIO_EN_SPK_AMP, 0); + gpio_output(GPIO_XHCI_DONE, 0); +} + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP); +} + +int tis_plat_irq_status(void) +{ + return gpio_eint_poll(GPIO_H1_AP_INT); +} diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c index 2be0b6d..c5fc117 100644 --- a/src/mainboard/google/asurada/chromeos.c +++ b/src/mainboard/google/asurada/chromeos.c @@ -1,25 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> #include <gpio.h> -#include <security/tpm/tis.h> #include "gpio.h" -void setup_chromeos_gpios(void) -{ - gpio_input(GPIO_WP); - gpio_input_pullup(GPIO_EC_AP_INT); - gpio_input_pullup(GPIO_EC_IN_RW); - gpio_input_pullup(GPIO_H1_AP_INT); - gpio_input_pullup(GPIO_SD_CD); - gpio_output(GPIO_RESET, 0); - gpio_output(GPIO_EN_SPK_AMP, 0); - gpio_output(GPIO_XHCI_DONE, 0); -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -31,13 +17,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP); -} - -int tis_plat_irq_status(void) -{ - return gpio_eint_poll(GPIO_H1_AP_INT); -} diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index c40f21c..8aaa243 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -1,10 +1,9 @@ bootblock-y += bootblock.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += ec.c diff --git a/src/mainboard/google/brya/bootmode.c b/src/mainboard/google/brya/bootmode.c new file mode 100644 index 0000000..85f85ee --- /dev/null +++ b/src/mainboard/google/brya/bootmode.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <bootmode.h> +#include <gpio.h> + +int get_write_protect_state(void) +{ + return gpio_get(GPIO_PCH_WP); +} diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c index 07fa56a..ce2b838 100644 --- a/src/mainboard/google/brya/chromeos.c +++ b/src/mainboard/google/brya/chromeos.c @@ -16,8 +16,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return gpio_get(GPIO_PCH_WP); -} diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc index e1e363c..6f98d44 100644 --- a/src/mainboard/google/cherry/Makefile.inc +++ b/src/mainboard/google/cherry/Makefile.inc @@ -1,21 +1,19 @@ bootblock-y += memlayout.ld bootblock-y += bootblock.c -bootblock-y += chromeos.c verstage-y += memlayout.ld -verstage-y += chromeos.c verstage-y += reset.c romstage-y += memlayout.ld romstage-y += boardid.c -romstage-y += chromeos.c romstage-y += regulator.c romstage-y += romstage.c romstage-y += sdram_configs.c +all-y += bootmode.c ramstage-y += memlayout.ld ramstage-y += boardid.c -ramstage-y += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += regulator.c ramstage-y += reset.c diff --git a/src/mainboard/google/cherry/bootmode.c b/src/mainboard/google/cherry/bootmode.c new file mode 100644 index 0000000..cba1e85 --- /dev/null +++ b/src/mainboard/google/cherry/bootmode.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> +#include <security/tpm/tis.h> + +#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_EC_AP_INT); + gpio_input_pullup(GPIO_SD_CD); + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_GSC_AP_INT); + gpio_output(GPIO_EN_SPK, 0); + gpio_output(GPIO_RESET, 0); + gpio_output(GPIO_XHCI_DONE, 0); + if (CONFIG(CHERRY_USE_RT1019)) + gpio_output(GPIO_BEEP_ON, 0); + else if (CONFIG(CHERRY_USE_RT1011)) + gpio_output(GPIO_RST_RT1011, 0); + +} + +int tis_plat_irq_status(void) +{ + return gpio_eint_poll(GPIO_GSC_AP_INT); +} diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c index 93e2df0..56e92e9 100644 --- a/src/mainboard/google/cherry/chromeos.c +++ b/src/mainboard/google/cherry/chromeos.c @@ -1,30 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> #include <gpio.h> -#include <security/tpm/tis.h> #include "gpio.h" -void setup_chromeos_gpios(void) -{ - gpio_input(GPIO_WP); - gpio_input_pullup(GPIO_EC_AP_INT); - gpio_input_pullup(GPIO_SD_CD); - gpio_input_pullup(GPIO_EC_IN_RW); - gpio_input_pullup(GPIO_GSC_AP_INT); - gpio_output(GPIO_EN_SPK, 0); - gpio_output(GPIO_RESET, 0); - gpio_output(GPIO_XHCI_DONE, 0); - if (CONFIG(CHERRY_USE_RT1019)) - gpio_output(GPIO_BEEP_ON, 0); - else if (CONFIG(CHERRY_USE_RT1011)) - gpio_output(GPIO_RST_RT1011, 0); - -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -55,8 +36,3 @@ else if (CONFIG(CHERRY_USE_RT1011)) lb_add_gpios(gpios, rt1011_gpios, ARRAY_SIZE(rt1011_gpios)); } - -int tis_plat_irq_status(void) -{ - return gpio_eint_poll(GPIO_GSC_AP_INT); -} diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc index 4720dc5..d036236 100644 --- a/src/mainboard/google/corsola/Makefile.inc +++ b/src/mainboard/google/corsola/Makefile.inc @@ -1,16 +1,12 @@ bootblock-y += memlayout.ld bootblock-y += bootblock.c -bootblock-y += chromeos.c verstage-y += memlayout.ld -verstage-y += chromeos.c verstage-y += reset.c romstage-y += memlayout.ld -romstage-y += chromeos.c romstage-y += romstage.c ramstage-y += memlayout.ld -ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/bootmode.c similarity index 100% rename from src/mainboard/google/corsola/chromeos.c rename to src/mainboard/google/corsola/bootmode.c diff --git a/src/mainboard/google/daisy/Makefile.inc b/src/mainboard/google/daisy/Makefile.inc index 4f5f87b..310023d 100644 --- a/src/mainboard/google/daisy/Makefile.inc +++ b/src/mainboard/google/daisy/Makefile.inc @@ -5,7 +5,7 @@ romstage-y += memory.c romstage-y += romstage.c romstage-y += wakeup.c -romstage-y += chromeos.c +all-y += bootmode.c ramstage-y += mainboard.c -ramstage-y += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/daisy/bootmode.c b/src/mainboard/google/daisy/bootmode.c new file mode 100644 index 0000000..d2d9582 --- /dev/null +++ b/src/mainboard/google/daisy/bootmode.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <soc/cpu.h> +#include <soc/gpio.h> +#include <bootmode.h> + +int get_recovery_mode_switch(void) +{ + uint64_t ec_events; + + /* The GPIO is active low. */ + if (!gpio_get_value(GPIO_Y10)) // RECMODE_GPIO + return 1; + + ec_events = google_chromeec_get_events_b(); + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int get_write_protect_state(void) +{ + return !gpio_get_value(GPIO_D16); +} diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 1edbc64..6e694d8 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -20,21 +20,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_recovery_mode_switch(void) -{ - uint64_t ec_events; - - /* The GPIO is active low. */ - if (!gpio_get_value(GPIO_Y10)) // RECMODE_GPIO - return 1; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); -} - -int get_write_protect_state(void) -{ - return !gpio_get_value(GPIO_D16); -} diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc index 290f2a3..60b7f55 100644 --- a/src/mainboard/google/dedede/Makefile.inc +++ b/src/mainboard/google/dedede/Makefile.inc @@ -1,10 +1,6 @@ bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c - -romstage-$(CONFIG_CHROMEOS) += chromeos.c - +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += ec.c diff --git a/src/mainboard/google/dedede/bootmode.c b/src/mainboard/google/dedede/bootmode.c new file mode 100644 index 0000000..85f85ee --- /dev/null +++ b/src/mainboard/google/dedede/bootmode.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <bootmode.h> +#include <gpio.h> + +int get_write_protect_state(void) +{ + return gpio_get(GPIO_PCH_WP); +} diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index 07fa56a..ce2b838 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -16,8 +16,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return gpio_get(GPIO_PCH_WP); -} diff --git a/src/mainboard/google/eve/Makefile.inc b/src/mainboard/google/eve/Makefile.inc index fc6dc66..eb602f0 100644 --- a/src/mainboard/google/eve/Makefile.inc +++ b/src/mainboard/google/eve/Makefile.inc @@ -4,9 +4,7 @@ bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/eve/bootmode.c b/src/mainboard/google/eve/bootmode.c new file mode 100644 index 0000000..01f3543 --- /dev/null +++ b/src/mainboard/google/eve/bootmode.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> +#include <soc/gpio.h> + +#include "gpio.h" + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index a746b8e..236741e 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -21,12 +21,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/fizz/Makefile.inc b/src/mainboard/google/fizz/Makefile.inc index e192cff..14c9c6d 100644 --- a/src/mainboard/google/fizz/Makefile.inc +++ b/src/mainboard/google/fizz/Makefile.inc @@ -1,12 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c - -romstage-$(CONFIG_CHROMEOS) += chromeos.c - +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/fizz/bootmode.c b/src/mainboard/google/fizz/bootmode.c new file mode 100644 index 0000000..335d7d3 --- /dev/null +++ b/src/mainboard/google/fizz/bootmode.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> +#include <soc/gpio.h> + +#include <variant/gpio.h> + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index f2f0b50..1d7171e 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -19,9 +19,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} diff --git a/src/mainboard/google/foster/Makefile.inc b/src/mainboard/google/foster/Makefile.inc index 7deae3e..f7eb3bb 100644 --- a/src/mainboard/google/foster/Makefile.inc +++ b/src/mainboard/google/foster/Makefile.inc @@ -14,16 +14,15 @@ bootblock-y += pmic.c bootblock-y += reset.c -verstage-y += chromeos.c verstage-y += reset.c romstage-y += reset.c romstage-y += romstage.c -romstage-y += chromeos.c romstage-y += sdram_configs.c +all-y += bootmode.c ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-y += reset.c -ramstage-y += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += sdram_configs.c diff --git a/src/mainboard/google/foster/bootmode.c b/src/mainboard/google/foster/bootmode.c new file mode 100644 index 0000000..358dbbd --- /dev/null +++ b/src/mainboard/google/foster/bootmode.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> + +int get_recovery_mode_switch(void) +{ + return 0; +} + diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index e06d72d..d7b88c2 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> #include <gpio.h> @@ -17,8 +16,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_recovery_mode_switch(void) -{ - return 0; -} diff --git a/src/mainboard/google/gale/Makefile.inc b/src/mainboard/google/gale/Makefile.inc index f23f804..dc2d705 100644 --- a/src/mainboard/google/gale/Makefile.inc +++ b/src/mainboard/google/gale/Makefile.inc @@ -7,7 +7,6 @@ verstage-y += boardid.c verstage-y += cdp.c -verstage-y += chromeos.c verstage-y += blsp.c verstage-y += reset.c verstage-y += verstage.c @@ -15,14 +14,14 @@ romstage-y += romstage.c romstage-y += boardid.c romstage-y += cdp.c -romstage-y += chromeos.c romstage-y += mmu.c romstage-y += reset.c romstage-y += blsp.c +all-y += bootmode.c ramstage-y += boardid.c ramstage-y += cdp.c -ramstage-y += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += mmu.c ramstage-y += reset.c diff --git a/src/mainboard/google/gale/bootmode.c b/src/mainboard/google/gale/bootmode.c new file mode 100644 index 0000000..e1e2d65 --- /dev/null +++ b/src/mainboard/google/gale/bootmode.c @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <bootmode.h> +#include <console/console.h> +#include <delay.h> +#include <drivers/i2c/ww_ring/ww_ring.h> +#include <gpio.h> +#include <soc/cdp.h> +#include <soc/blsp.h> +#include <timer.h> + +#define PP_SW 41 + +static int get_rec_sw_gpio_pin(void) +{ + uint8_t board_rev = board_id(); + + switch (board_rev) { + case BOARD_ID_GALE_PROTO: + case BOARD_ID_GALE_EVT: + case BOARD_ID_GALE_EVT2_0: + case BOARD_ID_GALE_EVT2_1: + return 7; + case BOARD_ID_GALE_EVT3: + default: + return 57; + } +} + +static int get_wp_status_gpio_pin(void) +{ + uint8_t board_rev = board_id(); + switch (board_rev) { + case BOARD_ID_GALE_PROTO: + case BOARD_ID_GALE_EVT: + case BOARD_ID_GALE_EVT2_0: + case BOARD_ID_GALE_EVT2_1: + return 6; + case BOARD_ID_GALE_EVT3: + default: + return 53; + } +} +static int read_gpio(gpio_t gpio_num) +{ + gpio_tlmm_config_set(gpio_num, GPIO_FUNC_DISABLE, + GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE); + udelay(10); /* Should be enough to settle. */ + return gpio_get(gpio_num); +} + +/* + * The recovery switch on storm is overloaded: it needs to be pressed for a + * certain duration at startup to signal different requests: + * + * - keeping it pressed for 8 to 16 seconds after startup signals the need for + * factory reset (wipeout); + * - keeping it pressed for longer than 16 seconds signals the need for Chrome + * OS recovery. + * + * The state is read once and cached for following inquiries. The below enum + * lists possible states. + */ +enum switch_state { + not_probed = -1, + no_req, + recovery_req, + wipeout_req +}; + +static void display_pattern(int pattern) +{ + ww_ring_display_pattern(BLSP_QUP_ID_3, pattern); +} + +#define WIPEOUT_MODE_DELAY_MS (8 * 1000) +#define RECOVERY_MODE_EXTRA_DELAY_MS (8 * 1000) + +static enum switch_state get_switch_state(void) +{ + struct stopwatch sw; + int sampled_value; + uint8_t rec_sw; + static enum switch_state saved_state = not_probed; + + if (saved_state != not_probed) + return saved_state; + + rec_sw = get_rec_sw_gpio_pin(); + sampled_value = !read_gpio(rec_sw); + + if (!sampled_value) { + saved_state = no_req; + display_pattern(WWR_NORMAL_BOOT); + return saved_state; + } + + display_pattern(WWR_RECOVERY_PUSHED); + printk(BIOS_INFO, "recovery button pressed\n"); + + stopwatch_init_msecs_expire(&sw, WIPEOUT_MODE_DELAY_MS); + + do { + sampled_value = !read_gpio(rec_sw); + if (!sampled_value) + break; + } while (!stopwatch_expired(&sw)); + + if (sampled_value) { + display_pattern(WWR_WIPEOUT_REQUEST); + printk(BIOS_INFO, "wipeout requested, checking recovery\n"); + stopwatch_init_msecs_expire(&sw, RECOVERY_MODE_EXTRA_DELAY_MS); + do { + sampled_value = !read_gpio(rec_sw); + if (!sampled_value) + break; + } while (!stopwatch_expired(&sw)); + + if (sampled_value) { + saved_state = recovery_req; + display_pattern(WWR_RECOVERY_REQUEST); + printk(BIOS_INFO, "recovery requested\n"); + } else { + saved_state = wipeout_req; + } + } else { + saved_state = no_req; + display_pattern(WWR_NORMAL_BOOT); + } + + return saved_state; +} + +int get_recovery_mode_switch(void) +{ + return get_switch_state() == recovery_req; +} + +int get_wipeout_mode_switch(void) +{ + return get_switch_state() == wipeout_req; +} + +int get_write_protect_state(void) +{ + return !read_gpio(get_wp_status_gpio_pin()); +} diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 82c7407..9e24e93 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -14,36 +14,6 @@ #define PP_SW 41 -static int get_rec_sw_gpio_pin(void) -{ - uint8_t board_rev = board_id(); - - switch (board_rev) { - case BOARD_ID_GALE_PROTO: - case BOARD_ID_GALE_EVT: - case BOARD_ID_GALE_EVT2_0: - case BOARD_ID_GALE_EVT2_1: - return 7; - case BOARD_ID_GALE_EVT3: - default: - return 57; - } -} - -static int get_wp_status_gpio_pin(void) -{ - uint8_t board_rev = board_id(); - switch (board_rev) { - case BOARD_ID_GALE_PROTO: - case BOARD_ID_GALE_EVT: - case BOARD_ID_GALE_EVT2_0: - case BOARD_ID_GALE_EVT2_1: - return 6; - case BOARD_ID_GALE_EVT3: - default: - return 53; - } -} static int read_gpio(gpio_t gpio_num) { gpio_tlmm_config_set(gpio_num, GPIO_FUNC_DISABLE, @@ -61,100 +31,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -/* - * The recovery switch on storm is overloaded: it needs to be pressed for a - * certain duration at startup to signal different requests: - * - * - keeping it pressed for 8 to 16 seconds after startup signals the need for - * factory reset (wipeout); - * - keeping it pressed for longer than 16 seconds signals the need for Chrome - * OS recovery. - * - * The state is read once and cached for following inquiries. The below enum - * lists possible states. - */ -enum switch_state { - not_probed = -1, - no_req, - recovery_req, - wipeout_req -}; - -static void display_pattern(int pattern) -{ - ww_ring_display_pattern(BLSP_QUP_ID_3, pattern); -} - -#define WIPEOUT_MODE_DELAY_MS (8 * 1000) -#define RECOVERY_MODE_EXTRA_DELAY_MS (8 * 1000) - -static enum switch_state get_switch_state(void) -{ - struct stopwatch sw; - int sampled_value; - uint8_t rec_sw; - static enum switch_state saved_state = not_probed; - - if (saved_state != not_probed) - return saved_state; - - rec_sw = get_rec_sw_gpio_pin(); - sampled_value = !read_gpio(rec_sw); - - if (!sampled_value) { - saved_state = no_req; - display_pattern(WWR_NORMAL_BOOT); - return saved_state; - } - - display_pattern(WWR_RECOVERY_PUSHED); - printk(BIOS_INFO, "recovery button pressed\n"); - - stopwatch_init_msecs_expire(&sw, WIPEOUT_MODE_DELAY_MS); - - do { - sampled_value = !read_gpio(rec_sw); - if (!sampled_value) - break; - } while (!stopwatch_expired(&sw)); - - if (sampled_value) { - display_pattern(WWR_WIPEOUT_REQUEST); - printk(BIOS_INFO, "wipeout requested, checking recovery\n"); - stopwatch_init_msecs_expire(&sw, RECOVERY_MODE_EXTRA_DELAY_MS); - do { - sampled_value = !read_gpio(rec_sw); - if (!sampled_value) - break; - } while (!stopwatch_expired(&sw)); - - if (sampled_value) { - saved_state = recovery_req; - display_pattern(WWR_RECOVERY_REQUEST); - printk(BIOS_INFO, "recovery requested\n"); - } else { - saved_state = wipeout_req; - } - } else { - saved_state = no_req; - display_pattern(WWR_NORMAL_BOOT); - } - - return saved_state; -} - -int get_recovery_mode_switch(void) -{ - return get_switch_state() == recovery_req; -} - -int get_wipeout_mode_switch(void) -{ - return get_switch_state() == wipeout_req; -} - -int get_write_protect_state(void) -{ - return !read_gpio(get_wp_status_gpio_pin()); -} diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc index 9fd41f8..f80c906 100644 --- a/src/mainboard/google/glados/Makefile.inc +++ b/src/mainboard/google/glados/Makefile.inc @@ -6,9 +6,7 @@ romstage-y += spd/spd.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c diff --git a/src/mainboard/google/glados/bootmode.c b/src/mainboard/google/glados/bootmode.c new file mode 100644 index 0000000..ffa653e --- /dev/null +++ b/src/mainboard/google/glados/bootmode.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 354db88..a303a16 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -20,12 +20,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc index b800945..e7f220f 100644 --- a/src/mainboard/google/gru/Makefile.inc +++ b/src/mainboard/google/gru/Makefile.inc @@ -3,23 +3,21 @@ subdirs-y += sdram_params/ bootblock-y += bootblock.c -bootblock-y += chromeos.c bootblock-y += pwm_regulator.c bootblock-y += boardid.c bootblock-y += reset.c -verstage-y += chromeos.c verstage-y += reset.c romstage-y += boardid.c -romstage-y += chromeos.c romstage-y += pwm_regulator.c romstage-y += romstage.c romstage-y += reset.c romstage-y += sdram_configs.c +all-y += bootmode.c ramstage-y += boardid.c -ramstage-y += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c ramstage-y += sdram_configs.c # Needed for ram_code() diff --git a/src/mainboard/google/gru/bootmode.c b/src/mainboard/google/gru/bootmode.c new file mode 100644 index 0000000..f8dd3f0 --- /dev/null +++ b/src/mainboard/google/gru/bootmode.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> +#include <security/tpm/tis.h> + +#include "board.h" + +static const uint32_t wp_polarity = CONFIG(GRU_BASEBOARD_SCARLET) ? + ACTIVE_LOW : ACTIVE_HIGH; + +int get_write_protect_state(void) +{ + return gpio_get(GPIO_WP) ^ !wp_polarity; +} + +void setup_chromeos_gpios(void) +{ + if (CONFIG(GRU_BASEBOARD_SCARLET)) + gpio_input(GPIO_WP); + else + gpio_input_pullup(GPIO_WP); + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_EC_IRQ); +} + +#if CONFIG(GRU_HAS_TPM2) +int tis_plat_irq_status(void) +{ + return gpio_irq_status(GPIO_TPM_IRQ); +} +#endif diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index fd3b988..2db36a8 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -1,21 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> #include <gpio.h> -#include <security/tpm/tis.h> #include "board.h" -static const uint32_t wp_polarity = CONFIG(GRU_BASEBOARD_SCARLET) ? - ACTIVE_LOW : ACTIVE_HIGH; - -int get_write_protect_state(void) -{ - return gpio_get(GPIO_WP) ^ !wp_polarity; -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,20 +23,3 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -void setup_chromeos_gpios(void) -{ - if (CONFIG(GRU_BASEBOARD_SCARLET)) - gpio_input(GPIO_WP); - else - gpio_input_pullup(GPIO_WP); - gpio_input_pullup(GPIO_EC_IN_RW); - gpio_input_pullup(GPIO_EC_IRQ); -} - -#if CONFIG(GRU_HAS_TPM2) -int tis_plat_irq_status(void) -{ - return gpio_irq_status(GPIO_TPM_IRQ); -} -#endif diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index debe942..ad1dc68 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -1,17 +1,15 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-y += ramstage.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += romstage_spd_smbus.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/hatch/bootmode.c b/src/mainboard/google/hatch/bootmode.c new file mode 100644 index 0000000..09bc73b --- /dev/null +++ b/src/mainboard/google/hatch/bootmode.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> +#include <variant/gpio.h> + +int get_write_protect_state(void) +{ + return gpio_get(GPIO_PCH_WP); +} diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index 02df63f..01e3155 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -19,8 +19,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return gpio_get(GPIO_PCH_WP); -} diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc index 9470592..d8dbbfc 100644 --- a/src/mainboard/google/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/Makefile.inc @@ -5,15 +5,14 @@ bootblock-y += ec.c romstage-y += BiosCallOuts.c -romstage-y += chromeos.c romstage-y += OemCustomize.c ramstage-y += BiosCallOuts.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += OemCustomize.c -verstage-y += chromeos.c verstage-y += ec.c subdirs-y += variants/baseboard diff --git a/src/mainboard/google/kahlee/bootmode.c b/src/mainboard/google/kahlee/bootmode.c new file mode 100644 index 0000000..2abe7c6 --- /dev/null +++ b/src/mainboard/google/kahlee/bootmode.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> +#include <variant/gpio.h> + +int get_write_protect_state(void) +{ + /* Write protect is active low, so invert it here */ + return !gpio_get(CROS_WP_GPIO); +} + diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 6efa2fa..9b92656 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -19,12 +19,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Write protect is active low, so invert it here */ - return !gpio_get(CROS_WP_GPIO); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 968ee19..85642a5 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -4,20 +4,19 @@ bootblock-y += bootblock.c bootblock-y += reset.c -verstage-y += chromeos.c verstage-y += early_init.c verstage-y += reset.c verstage-y += verstage.c romstage-y += boardid.c -romstage-y += chromeos.c romstage-y += early_init.c romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c +all-y += bootmode.c ramstage-y += boardid.c -ramstage-y += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel_flapjack.c ramstage-$(CONFIG_BOARD_GOOGLE_KAKADU) += panel_kakadu.c diff --git a/src/mainboard/google/kukui/bootmode.c b/src/mainboard/google/kukui/bootmode.c new file mode 100644 index 0000000..c414d1b --- /dev/null +++ b/src/mainboard/google/kukui/bootmode.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> +#include <security/tpm/tis.h> + +#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(EC_IN_RW); + gpio_input_pullup(EC_IRQ); + gpio_input_pullup(CR50_IRQ); + gpio_output(GPIO_RESET, 0); + gpio_output(GPIO_EN_SPK_AMP, 0); +} + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP); +} + +int tis_plat_irq_status(void) +{ + return gpio_eint_poll(CR50_IRQ); +} diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 1615328..d750b78 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -1,23 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> #include <gpio.h> -#include <security/tpm/tis.h> #include "gpio.h" -void setup_chromeos_gpios(void) -{ - gpio_input(GPIO_WP); - gpio_input_pullup(EC_IN_RW); - gpio_input_pullup(EC_IRQ); - gpio_input_pullup(CR50_IRQ); - gpio_output(GPIO_RESET, 0); - gpio_output(GPIO_EN_SPK_AMP, 0); -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -28,13 +16,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP); -} - -int tis_plat_irq_status(void) -{ - return gpio_eint_poll(CR50_IRQ); -} diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc index 190cfc5..fcb46f2 100644 --- a/src/mainboard/google/nyan/Makefile.inc +++ b/src/mainboard/google/nyan/Makefile.inc @@ -18,14 +18,13 @@ romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += early_configs.c +all-y += bootmode.c ramstage-y += reset.c ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += reset.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += early_configs.c diff --git a/src/mainboard/google/nyan/bootmode.c b/src/mainboard/google/nyan/bootmode.c new file mode 100644 index 0000000..3c30cf8 --- /dev/null +++ b/src/mainboard/google/nyan/bootmode.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO(R1)); +} diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 4d77c8a..8ffeb86 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -15,8 +15,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO(R1)); -} diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc index b734b5b..6c31980 100644 --- a/src/mainboard/google/nyan_big/Makefile.inc +++ b/src/mainboard/google/nyan_big/Makefile.inc @@ -17,14 +17,13 @@ romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += early_configs.c +all-y += bootmode.c ramstage-y += reset.c ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += reset.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += early_configs.c diff --git a/src/mainboard/google/nyan_big/bootmode.c b/src/mainboard/google/nyan_big/bootmode.c new file mode 100644 index 0000000..3c30cf8 --- /dev/null +++ b/src/mainboard/google/nyan_big/bootmode.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO(R1)); +} diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 4d77c8a..8ffeb86 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -15,8 +15,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO(R1)); -} diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc index 54410f0..7227895 100644 --- a/src/mainboard/google/nyan_blaze/Makefile.inc +++ b/src/mainboard/google/nyan_blaze/Makefile.inc @@ -14,7 +14,6 @@ bootblock-y += pmic.c bootblock-y += reset.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += early_configs.c verstage-y += reset.c @@ -22,9 +21,9 @@ romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += reset.c ramstage-y += boardid.c ramstage-y += mainboard.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/nyan_blaze/bootmode.c b/src/mainboard/google/nyan_blaze/bootmode.c new file mode 100644 index 0000000..3c30cf8 --- /dev/null +++ b/src/mainboard/google/nyan_blaze/bootmode.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO(R1)); +} diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 4d77c8a..8ffeb86 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -15,8 +15,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO(R1)); -} diff --git a/src/mainboard/google/oak/Makefile.inc b/src/mainboard/google/oak/Makefile.inc index 79a80ee..b53885f 100644 --- a/src/mainboard/google/oak/Makefile.inc +++ b/src/mainboard/google/oak/Makefile.inc @@ -1,19 +1,17 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c -bootblock-y += chromeos.c bootblock-y += boardid.c bootblock-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c -verstage-y += chromeos.c verstage-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c -romstage-y += chromeos.c romstage-y += romstage.c sdram_configs.c romstage-y += boardid.c romstage-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c +all-y += bootmode.c ramstage-y += mainboard.c -ramstage-y += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += boardid.c ramstage-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c diff --git a/src/mainboard/google/oak/bootmode.c b/src/mainboard/google/oak/bootmode.c new file mode 100644 index 0000000..8e55404 --- /dev/null +++ b/src/mainboard/google/oak/bootmode.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <bootmode.h> +#include <gpio.h> + +#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(WRITE_PROTECT); + gpio_input_pullup(EC_IN_RW); + gpio_input_pullup(EC_IRQ); + gpio_input(LID); + gpio_input_pullup(POWER_BUTTON); + if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5) + gpio_output(EC_SUSPEND_L, 1); +} + +int get_write_protect_state(void) +{ + return !gpio_get(WRITE_PROTECT); +} diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index 36e801b..01529dc 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -8,17 +8,6 @@ #include "gpio.h" -void setup_chromeos_gpios(void) -{ - gpio_input(WRITE_PROTECT); - gpio_input_pullup(EC_IN_RW); - gpio_input_pullup(EC_IRQ); - gpio_input(LID); - gpio_input_pullup(POWER_BUTTON); - if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5) - gpio_output(EC_SUSPEND_L, 1); -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -30,8 +19,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(WRITE_PROTECT); -} diff --git a/src/mainboard/google/octopus/Makefile.inc b/src/mainboard/google/octopus/Makefile.inc index 1acd8c6..3a7b230 100644 --- a/src/mainboard/google/octopus/Makefile.inc +++ b/src/mainboard/google/octopus/Makefile.inc @@ -1,13 +1,11 @@ bootblock-y += bootblock.c bootblock-y += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c - +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/octopus/bootmode.c b/src/mainboard/google/octopus/bootmode.c new file mode 100644 index 0000000..15d216d --- /dev/null +++ b/src/mainboard/google/octopus/bootmode.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +int get_write_protect_state(void) +{ + return gpio_get(GPIO_PCH_WP); +} diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index 0f831d4..757634d 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -19,8 +19,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return gpio_get(GPIO_PCH_WP); -} diff --git a/src/mainboard/google/peach_pit/Makefile.inc b/src/mainboard/google/peach_pit/Makefile.inc index 4f5f87b..310023d 100644 --- a/src/mainboard/google/peach_pit/Makefile.inc +++ b/src/mainboard/google/peach_pit/Makefile.inc @@ -5,7 +5,7 @@ romstage-y += memory.c romstage-y += romstage.c romstage-y += wakeup.c -romstage-y += chromeos.c +all-y += bootmode.c ramstage-y += mainboard.c -ramstage-y += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/peach_pit/bootmode.c b/src/mainboard/google/peach_pit/bootmode.c new file mode 100644 index 0000000..48cee25 --- /dev/null +++ b/src/mainboard/google/peach_pit/bootmode.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <soc/cpu.h> +#include <soc/gpio.h> + +int get_recovery_mode_switch(void) +{ + uint64_t ec_events; + + /* The GPIO is active low. */ + if (!gpio_get_value(GPIO_X07)) // RECMODE_GPIO + return 1; + + ec_events = google_chromeec_get_events_b(); + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int get_write_protect_state(void) +{ + return !gpio_get_value(GPIO_X30); +} diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index ec3868e..a983f3b 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -20,21 +20,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_recovery_mode_switch(void) -{ - uint64_t ec_events; - - /* The GPIO is active low. */ - if (!gpio_get_value(GPIO_X07)) // RECMODE_GPIO - return 1; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); -} - -int get_write_protect_state(void) -{ - return !gpio_get_value(GPIO_X30); -} diff --git a/src/mainboard/google/poppy/Makefile.inc b/src/mainboard/google/poppy/Makefile.inc index 9f36e79..2c76b90 100644 --- a/src/mainboard/google/poppy/Makefile.inc +++ b/src/mainboard/google/poppy/Makefile.inc @@ -1,12 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c - -romstage-$(CONFIG_CHROMEOS) += chromeos.c - +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/poppy/bootmode.c b/src/mainboard/google/poppy/bootmode.c new file mode 100644 index 0000000..335d7d3 --- /dev/null +++ b/src/mainboard/google/poppy/bootmode.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> +#include <soc/gpio.h> + +#include <variant/gpio.h> + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 6095584..842942e 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -23,9 +23,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index e0d5524..e36eb8a 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -1,12 +1,12 @@ ## SPDX-License-Identifier: GPL-2.0-only -romstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += irqroute.c ramstage-y += w25q64.c -ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/bootmode.c ramstage-$(CONFIG_BOARD_GOOGLE_NINJA) += variants/$(VARIANT_DIR)/lan.c ramstage-$(CONFIG_BOARD_GOOGLE_SUMO) += variants/$(VARIANT_DIR)/lan.c diff --git a/src/mainboard/google/rambi/bootmode.c b/src/mainboard/google/rambi/bootmode.c new file mode 100644 index 0000000..586ea04 --- /dev/null +++ b/src/mainboard/google/rambi/bootmode.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <soc/gpio.h> + +/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ +#define WP_STATUS_PAD 36 + +int get_write_protect_state(void) +{ + /* + * The vboot loader queries this function in romstage. The GPIOs have + * not been set up yet as that configuration is done in ramstage. The + * hardware defaults to an input but there is a 20K pulldown. Externally + * there is a 10K pullup. Disable the internal pull in romstage so that + * there isn't any ambiguity in the reading. + */ + if (ENV_ROMSTAGE) + ssus_disable_internal_pull(WP_STATUS_PAD); + + /* WP is enabled when the pin is reading high. */ + return ssus_get_gpio(WP_STATUS_PAD); +} + diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 494b3d3..11e9e60 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -6,9 +6,6 @@ #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ -#define WP_STATUS_PAD 36 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -19,22 +16,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* - * The vboot loader queries this function in romstage. The GPIOs have - * not been set up yet as that configuration is done in ramstage. The - * hardware defaults to an input but there is a 20K pulldown. Externally - * there is a 10K pullup. Disable the internal pull in romstage so that - * there isn't any ambiguity in the reading. - */ - if (ENV_ROMSTAGE) - ssus_disable_internal_pull(WP_STATUS_PAD); - - /* WP is enabled when the pin is reading high. */ - return ssus_get_gpio(WP_STATUS_PAD); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc index dd49610..e9de169 100644 --- a/src/mainboard/google/reef/Makefile.inc +++ b/src/mainboard/google/reef/Makefile.inc @@ -1,13 +1,11 @@ bootblock-y += bootblock.c bootblock-y += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c - +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/reef/bootmode.c b/src/mainboard/google/reef/bootmode.c new file mode 100644 index 0000000..10e9775 --- /dev/null +++ b/src/mainboard/google/reef/bootmode.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index e30d3d2..22136ea 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -18,9 +18,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} diff --git a/src/mainboard/google/smaug/Makefile.inc b/src/mainboard/google/smaug/Makefile.inc index 32c66b9..85e1e92 100644 --- a/src/mainboard/google/smaug/Makefile.inc +++ b/src/mainboard/google/smaug/Makefile.inc @@ -14,16 +14,15 @@ bootblock-y += pmic.c bootblock-y += reset.c -verstage-y += chromeos.c verstage-y += reset.c -romstage-y += chromeos.c romstage-y += pmic.c romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-y += reset.c diff --git a/src/mainboard/google/smaug/bootmode.c b/src/mainboard/google/smaug/bootmode.c new file mode 100644 index 0000000..35c4cfd --- /dev/null +++ b/src/mainboard/google/smaug/bootmode.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> + +#include "gpio.h" + +int get_write_protect_state(void) +{ + return !gpio_get(WRITE_PROTECT_L); +} diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index 956e949..3f7b315 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -15,8 +15,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(WRITE_PROTECT_L); -} diff --git a/src/mainboard/google/storm/Makefile.inc b/src/mainboard/google/storm/Makefile.inc index b1bcacd..2a0f991 100644 --- a/src/mainboard/google/storm/Makefile.inc +++ b/src/mainboard/google/storm/Makefile.inc @@ -7,20 +7,19 @@ verstage-y += boardid.c verstage-y += cdp.c -verstage-y += chromeos.c verstage-y += gsbi.c verstage-y += reset.c romstage-y += romstage.c romstage-y += cdp.c -romstage-y += chromeos.c romstage-y += mmu.c romstage-y += reset.c romstage-y += gsbi.c +all-y += bootmode.c ramstage-y += boardid.c ramstage-y += cdp.c -ramstage-y += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += mmu.c ramstage-y += reset.c diff --git a/src/mainboard/google/storm/bootmode.c b/src/mainboard/google/storm/bootmode.c new file mode 100644 index 0000000..5a0eec4 --- /dev/null +++ b/src/mainboard/google/storm/bootmode.c @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <bootmode.h> +#include <console/console.h> +#include <delay.h> +#include <drivers/i2c/ww_ring/ww_ring.h> +#include <gpio.h> +#include <soc/cdp.h> +#include <soc/gsbi.h> +#include <timer.h> + +#define DEV_SW 15 +#define REC_SW 16 +#define WP_SW 17 + +static int read_gpio(gpio_t gpio_num) +{ + gpio_tlmm_config_set(gpio_num, GPIO_FUNC_DISABLE, + GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE); + udelay(10); /* Should be enough to settle. */ + return gpio_get(gpio_num); +} + +/* + * The recovery switch on storm is overloaded: it needs to be pressed for a + * certain duration at startup to signal different requests: + * + * - keeping it pressed for 8 to 16 seconds after startup signals the need for + * factory reset (wipeout); + * - keeping it pressed for longer than 16 seconds signals the need for Chrome + * OS recovery. + * + * The state is read once and cached for following inquiries. The below enum + * lists possible states. + */ +enum switch_state { + not_probed = -1, + no_req, + recovery_req, + wipeout_req +}; + +static void display_pattern(int pattern) +{ + if (board_id() == BOARD_ID_WHIRLWIND_SP5) + ww_ring_display_pattern(GSBI_ID_7, pattern); +} + +#define WIPEOUT_MODE_DELAY_MS (8 * 1000) +#define RECOVERY_MODE_EXTRA_DELAY_MS (8 * 1000) + +static enum switch_state get_switch_state(void) +{ + struct stopwatch sw; + int sampled_value; + static enum switch_state saved_state = not_probed; + + if (saved_state != not_probed) + return saved_state; + + sampled_value = !read_gpio(REC_SW); + + if (!sampled_value) { + saved_state = no_req; + display_pattern(WWR_NORMAL_BOOT); + return saved_state; + } + + display_pattern(WWR_RECOVERY_PUSHED); + printk(BIOS_INFO, "recovery button pressed\n"); + + stopwatch_init_msecs_expire(&sw, WIPEOUT_MODE_DELAY_MS); + + do { + sampled_value = !read_gpio(REC_SW); + if (!sampled_value) + break; + } while (!stopwatch_expired(&sw)); + + if (sampled_value) { + display_pattern(WWR_WIPEOUT_REQUEST); + printk(BIOS_INFO, "wipeout requested, checking recovery\n"); + stopwatch_init_msecs_expire(&sw, RECOVERY_MODE_EXTRA_DELAY_MS); + do { + sampled_value = !read_gpio(REC_SW); + if (!sampled_value) + break; + } while (!stopwatch_expired(&sw)); + + if (sampled_value) { + saved_state = recovery_req; + display_pattern(WWR_RECOVERY_REQUEST); + printk(BIOS_INFO, "recovery requested\n"); + } else { + saved_state = wipeout_req; + } + } else { + saved_state = no_req; + display_pattern(WWR_NORMAL_BOOT); + } + + return saved_state; +} + +int get_recovery_mode_switch(void) +{ + return get_switch_state() == recovery_req; +} + +int get_wipeout_mode_switch(void) +{ + return get_switch_state() == wipeout_req; +} + +int get_write_protect_state(void) +{ + return !read_gpio(WP_SW); +} diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index dc18fb8..8e6a268 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -33,99 +33,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -/* - * The recovery switch on storm is overloaded: it needs to be pressed for a - * certain duration at startup to signal different requests: - * - * - keeping it pressed for 8 to 16 seconds after startup signals the need for - * factory reset (wipeout); - * - keeping it pressed for longer than 16 seconds signals the need for Chrome - * OS recovery. - * - * The state is read once and cached for following inquiries. The below enum - * lists possible states. - */ -enum switch_state { - not_probed = -1, - no_req, - recovery_req, - wipeout_req -}; - -static void display_pattern(int pattern) -{ - if (board_id() == BOARD_ID_WHIRLWIND_SP5) - ww_ring_display_pattern(GSBI_ID_7, pattern); -} - -#define WIPEOUT_MODE_DELAY_MS (8 * 1000) -#define RECOVERY_MODE_EXTRA_DELAY_MS (8 * 1000) - -static enum switch_state get_switch_state(void) -{ - struct stopwatch sw; - int sampled_value; - static enum switch_state saved_state = not_probed; - - if (saved_state != not_probed) - return saved_state; - - sampled_value = !read_gpio(REC_SW); - - if (!sampled_value) { - saved_state = no_req; - display_pattern(WWR_NORMAL_BOOT); - return saved_state; - } - - display_pattern(WWR_RECOVERY_PUSHED); - printk(BIOS_INFO, "recovery button pressed\n"); - - stopwatch_init_msecs_expire(&sw, WIPEOUT_MODE_DELAY_MS); - - do { - sampled_value = !read_gpio(REC_SW); - if (!sampled_value) - break; - } while (!stopwatch_expired(&sw)); - - if (sampled_value) { - display_pattern(WWR_WIPEOUT_REQUEST); - printk(BIOS_INFO, "wipeout requested, checking recovery\n"); - stopwatch_init_msecs_expire(&sw, RECOVERY_MODE_EXTRA_DELAY_MS); - do { - sampled_value = !read_gpio(REC_SW); - if (!sampled_value) - break; - } while (!stopwatch_expired(&sw)); - - if (sampled_value) { - saved_state = recovery_req; - display_pattern(WWR_RECOVERY_REQUEST); - printk(BIOS_INFO, "recovery requested\n"); - } else { - saved_state = wipeout_req; - } - } else { - saved_state = no_req; - display_pattern(WWR_NORMAL_BOOT); - } - - return saved_state; -} - -int get_recovery_mode_switch(void) -{ - return get_switch_state() == recovery_req; -} - -int get_wipeout_mode_switch(void) -{ - return get_switch_state() == wipeout_req; -} - -int get_write_protect_state(void) -{ - return !read_gpio(WP_SW); -} diff --git a/src/mainboard/google/trogdor/Makefile.inc b/src/mainboard/google/trogdor/Makefile.inc index 9a71ea5..574b944 100644 --- a/src/mainboard/google/trogdor/Makefile.inc +++ b/src/mainboard/google/trogdor/Makefile.inc @@ -1,22 +1,20 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += boardid.c -bootblock-y += chromeos.c bootblock-y += bootblock.c ifneq ($(CONFIG_BOARD_GOOGLE_BUBS),y) verstage-y += reset.c endif verstage-y += boardid.c -verstage-y += chromeos.c romstage-y += romstage.c romstage-y += boardid.c -romstage-y += chromeos.c ramstage-y += mainboard.c ifneq ($(CONFIG_BOARD_GOOGLE_BUBS),y) ramstage-y += reset.c endif -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += boardid.c diff --git a/src/mainboard/google/trogdor/bootmode.c b/src/mainboard/google/trogdor/bootmode.c new file mode 100644 index 0000000..6f2c7cb --- /dev/null +++ b/src/mainboard/google/trogdor/bootmode.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include "board.h" +#include <security/tpm/tis.h> + +void setup_chromeos_gpios(void) +{ + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_AP_EC_INT); + gpio_input_pullup(GPIO_SD_CD_L); + gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); + gpio_output(GPIO_AMP_ENABLE, 0); + gpio_output(GPIO_BACKLIGHT_ENABLE, 0); + + if (CONFIG(TROGDOR_HAS_MIPI_PANEL)) { + gpio_output(GPIO_MIPI_1V8_ENABLE, 0); + gpio_output(GPIO_AVDD_LCD_ENABLE, 0); + gpio_output(GPIO_VDD_RESET_1V8, 0); + gpio_output(GPIO_AVEE_LCD_ENABLE, 0); + } else { + gpio_output(GPIO_EN_PP3300_DX_EDP, 0); + gpio_output(GPIO_EDP_BRIDGE_ENABLE, 0); + } + + if (CONFIG(TROGDOR_HAS_FINGERPRINT)) { + gpio_output(GPIO_FPMCU_BOOT0, 0); + gpio_output(GPIO_FP_RST_L, 0); + gpio_output(GPIO_EN_FP_RAILS, 0); + } +} + +int tis_plat_irq_status(void) +{ + return gpio_irq_status(GPIO_H1_AP_INT); +} diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 984f5a4..7de7c0c 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -2,35 +2,9 @@ #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <bootmode.h> +#include <gpio.h> + #include "board.h" -#include <security/tpm/tis.h> - -void setup_chromeos_gpios(void) -{ - gpio_input_pullup(GPIO_EC_IN_RW); - gpio_input_pullup(GPIO_AP_EC_INT); - gpio_input_pullup(GPIO_SD_CD_L); - gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); - gpio_output(GPIO_AMP_ENABLE, 0); - gpio_output(GPIO_BACKLIGHT_ENABLE, 0); - - if (CONFIG(TROGDOR_HAS_MIPI_PANEL)) { - gpio_output(GPIO_MIPI_1V8_ENABLE, 0); - gpio_output(GPIO_AVDD_LCD_ENABLE, 0); - gpio_output(GPIO_VDD_RESET_1V8, 0); - gpio_output(GPIO_AVEE_LCD_ENABLE, 0); - } else { - gpio_output(GPIO_EN_PP3300_DX_EDP, 0); - gpio_output(GPIO_EDP_BRIDGE_ENABLE, 0); - } - - if (CONFIG(TROGDOR_HAS_FINGERPRINT)) { - gpio_output(GPIO_FPMCU_BOOT0, 0); - gpio_output(GPIO_FP_RST_L, 0); - gpio_output(GPIO_EN_FP_RAILS, 0); - } -} void fill_lb_gpios(struct lb_gpios *gpios) { @@ -51,8 +25,3 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int tis_plat_irq_status(void) -{ - return gpio_irq_status(GPIO_H1_AP_INT); -} diff --git a/src/mainboard/google/veyron/Makefile.inc b/src/mainboard/google/veyron/Makefile.inc index 6c3b7f4..1cae8a5 100644 --- a/src/mainboard/google/veyron/Makefile.inc +++ b/src/mainboard/google/veyron/Makefile.inc @@ -2,20 +2,18 @@ bootblock-y += bootblock.c bootblock-y += boardid.c -bootblock-y += chromeos.c bootblock-y += reset.c verstage-y += boardid.c -verstage-y += chromeos.c verstage-y += reset.c romstage-y += boardid.c -romstage-y += chromeos.c romstage-y += romstage.c romstage-y += sdram_configs.c romstage-y += reset.c +all-y += bootmode.c ramstage-y += boardid.c -ramstage-y += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c diff --git a/src/mainboard/google/veyron/bootmode.c b/src/mainboard/google/veyron/bootmode.c new file mode 100644 index 0000000..bcf4fd1 --- /dev/null +++ b/src/mainboard/google/veyron/bootmode.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <gpio.h> + +#include "board.h" + +#define GPIO_WP GPIO(7, A, 6) +#define GPIO_LID GPIO(0, A, 6) +#define GPIO_POWER GPIO(0, A, 5) +#define GPIO_RECOVERY GPIO(0, B, 1) +#define GPIO_ECINRW GPIO(0, A, 7) +#define GPIO_ECIRQ GPIO(7, A, 7) + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_LID); + gpio_input(GPIO_POWER); + gpio_input_pullup(GPIO_RECOVERY); + gpio_input(GPIO_ECIRQ); +} + +int get_recovery_mode_switch(void) +{ + uint64_t ec_events; + + /* The GPIO is active low. */ + if (!gpio_get(GPIO_RECOVERY)) + return 1; + + ec_events = google_chromeec_get_events_b(); + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP); +} diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index 40c2d12..03a9fef 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -3,8 +3,6 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> #include <gpio.h> #include "board.h" @@ -16,15 +14,6 @@ #define GPIO_ECINRW GPIO(0, A, 7) #define GPIO_ECIRQ GPIO(7, A, 7) -void setup_chromeos_gpios(void) -{ - gpio_input(GPIO_WP); - gpio_input_pullup(GPIO_LID); - gpio_input(GPIO_POWER); - gpio_input_pullup(GPIO_RECOVERY); - gpio_input(GPIO_ECIRQ); -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -39,21 +28,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_recovery_mode_switch(void) -{ - uint64_t ec_events; - - /* The GPIO is active low. */ - if (!gpio_get(GPIO_RECOVERY)) - return 1; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); -} - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP); -} diff --git a/src/mainboard/google/veyron_mickey/Makefile.inc b/src/mainboard/google/veyron_mickey/Makefile.inc index 6c3b7f4..1cae8a5 100644 --- a/src/mainboard/google/veyron_mickey/Makefile.inc +++ b/src/mainboard/google/veyron_mickey/Makefile.inc @@ -2,20 +2,18 @@ bootblock-y += bootblock.c bootblock-y += boardid.c -bootblock-y += chromeos.c bootblock-y += reset.c verstage-y += boardid.c -verstage-y += chromeos.c verstage-y += reset.c romstage-y += boardid.c -romstage-y += chromeos.c romstage-y += romstage.c romstage-y += sdram_configs.c romstage-y += reset.c +all-y += bootmode.c ramstage-y += boardid.c -ramstage-y += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c diff --git a/src/mainboard/google/veyron_mickey/bootmode.c b/src/mainboard/google/veyron_mickey/bootmode.c new file mode 100644 index 0000000..f0396d0 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/bootmode.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> + +#include "board.h" + +#define GPIO_WP GPIO(7, A, 6) +#define GPIO_RECOVERY GPIO(0, B, 1) + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_RECOVERY); +} + +int get_recovery_mode_switch(void) +{ + return !gpio_get(GPIO_RECOVERY); +} + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP); +} diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index 0ef5c43..c1dbe47 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -7,15 +7,6 @@ #include "board.h" -#define GPIO_WP GPIO(7, A, 6) -#define GPIO_RECOVERY GPIO(0, B, 1) - -void setup_chromeos_gpios(void) -{ - gpio_input(GPIO_WP); - gpio_input_pullup(GPIO_RECOVERY); -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -25,13 +16,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_recovery_mode_switch(void) -{ - return !gpio_get(GPIO_RECOVERY); -} - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP); -} diff --git a/src/mainboard/google/veyron_rialto/Makefile.inc b/src/mainboard/google/veyron_rialto/Makefile.inc index 6c3b7f4..1cae8a5 100644 --- a/src/mainboard/google/veyron_rialto/Makefile.inc +++ b/src/mainboard/google/veyron_rialto/Makefile.inc @@ -2,20 +2,18 @@ bootblock-y += bootblock.c bootblock-y += boardid.c -bootblock-y += chromeos.c bootblock-y += reset.c verstage-y += boardid.c -verstage-y += chromeos.c verstage-y += reset.c romstage-y += boardid.c -romstage-y += chromeos.c romstage-y += romstage.c romstage-y += sdram_configs.c romstage-y += reset.c +all-y += bootmode.c ramstage-y += boardid.c -ramstage-y += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c diff --git a/src/mainboard/google/veyron_rialto/bootmode.c b/src/mainboard/google/veyron_rialto/bootmode.c new file mode 100644 index 0000000..6bcc0d0 --- /dev/null +++ b/src/mainboard/google/veyron_rialto/bootmode.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> + +#include "board.h" + +#define GPIO_WP GPIO(7, A, 6) +#define GPIO_POWER GPIO(0, A, 5) +#define GPIO_RECOVERY_SERVO GPIO(0, B, 1) +#define GPIO_RECOVERY_PUSHKEY GPIO(7, B, 1) + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input(GPIO_POWER); + gpio_input_pullup(GPIO_RECOVERY_SERVO); + gpio_input_pullup(GPIO_RECOVERY_PUSHKEY); +} + +int get_recovery_mode_switch(void) +{ + // Both RECOVERY_SERVO and RECOVERY_PUSHKEY are low active. + return !(gpio_get(GPIO_RECOVERY_SERVO) && + gpio_get(GPIO_RECOVERY_PUSHKEY)); +} + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP); +} diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 27f62b9..ab311ac 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -12,14 +12,6 @@ #define GPIO_RECOVERY_SERVO GPIO(0, B, 1) #define GPIO_RECOVERY_PUSHKEY GPIO(7, B, 1) -void setup_chromeos_gpios(void) -{ - gpio_input(GPIO_WP); - gpio_input(GPIO_POWER); - gpio_input_pullup(GPIO_RECOVERY_SERVO); - gpio_input_pullup(GPIO_RECOVERY_PUSHKEY); -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -32,15 +24,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_recovery_mode_switch(void) -{ - // Both RECOVERY_SERVO and RECOVERY_PUSHKEY are low active. - return !(gpio_get(GPIO_RECOVERY_SERVO) && - gpio_get(GPIO_RECOVERY_PUSHKEY)); -} - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP); -} diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc index 1847d56..89ab2b2 100644 --- a/src/mainboard/google/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/Makefile.inc @@ -3,15 +3,14 @@ bootblock-y += bootblock.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += mainboard.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/volteer/bootmode.c b/src/mainboard/google/volteer/bootmode.c new file mode 100644 index 0000000..8ca69ff --- /dev/null +++ b/src/mainboard/google/volteer/bootmode.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootmode.h> +#include <gpio.h> +#include <variant/gpio.h> + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index 88566e4..2204a19 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -17,9 +17,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc index ccc163c..7d4757f 100644 --- a/src/mainboard/google/zork/Makefile.inc +++ b/src/mainboard/google/zork/Makefile.inc @@ -2,11 +2,11 @@ bootblock-y += bootblock.c -romstage-y += chromeos.c romstage-y += sku_id.c romstage-y += romstage.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += sku_id.c diff --git a/src/mainboard/google/zork/bootmode.c b/src/mainboard/google/zork/bootmode.c new file mode 100644 index 0000000..7458190 --- /dev/null +++ b/src/mainboard/google/zork/bootmode.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootmode.h> +#include <gpio.h> +#include <variant/gpio.h> + +int get_write_protect_state(void) +{ + /* Write protect on zork is active low, so invert it here */ + return !gpio_get(CROS_WP_GPIO); +} + diff --git a/src/mainboard/google/zork/chromeos.c b/src/mainboard/google/zork/chromeos.c index 04e1d4b..230de2c 100644 --- a/src/mainboard/google/zork/chromeos.c +++ b/src/mainboard/google/zork/chromeos.c @@ -18,12 +18,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Write protect on zork is active low, so invert it here */ - return !gpio_get(CROS_WP_GPIO); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index 04c1645..7ec09e3 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += spd bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_M),y) bootblock-y += early_gpio_m.c ramstage-y += gpio_m.c @@ -12,13 +11,12 @@ ramstage-y += gpio.c endif -verstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c romstage-y += board_id.c romstage-y += memory.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/intel/adlrvp/bootmode.c b/src/mainboard/intel/adlrvp/bootmode.c new file mode 100644 index 0000000..2c8ec97 --- /dev/null +++ b/src/mainboard/intel/adlrvp/bootmode.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> + +#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} +#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ + diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c index 2bb4f73..1ea943e 100644 --- a/src/mainboard/intel/adlrvp/chromeos.c +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -19,16 +19,3 @@ else lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios) - 1); } - -#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) -int get_lid_switch(void) -{ - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - return 0; -} -#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ diff --git a/src/mainboard/intel/coffeelake_rvp/Makefile.inc b/src/mainboard/intel/coffeelake_rvp/Makefile.inc index 77f0691..19d6e52 100644 --- a/src/mainboard/intel/coffeelake_rvp/Makefile.inc +++ b/src/mainboard/intel/coffeelake_rvp/Makefile.inc @@ -1,13 +1,11 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += memory.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/intel/coffeelake_rvp/bootmode.c b/src/mainboard/intel/coffeelake_rvp/bootmode.c new file mode 100644 index 0000000..7709f94 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/bootmode.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> + +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 99ebbad..f232478 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -1,11 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <gpio.h> -#include <soc/gpio.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -16,14 +13,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_lid_switch(void) -{ - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - return 0; -} diff --git a/src/mainboard/intel/glkrvp/Makefile.inc b/src/mainboard/intel/glkrvp/Makefile.inc index 37b60d0..e718754 100644 --- a/src/mainboard/intel/glkrvp/Makefile.inc +++ b/src/mainboard/intel/glkrvp/Makefile.inc @@ -1,15 +1,14 @@ bootblock-y += bootblock.c bootblock-y += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += boardid.c +all-y += bootmode.c ramstage-y += boardid.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/glkrvp/bootmode.c b/src/mainboard/intel/glkrvp/bootmode.c new file mode 100644 index 0000000..a6efcd5 --- /dev/null +++ b/src/mainboard/intel/glkrvp/bootmode.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> + +int __weak get_lid_switch(void) +{ + return -1; +} diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 18177f0..9155953 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -18,8 +18,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int __weak get_lid_switch(void) -{ - return -1; -} diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc index 60551c5..00b051d 100644 --- a/src/mainboard/intel/icelake_rvp/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/Makefile.inc @@ -3,14 +3,12 @@ subdirs-y += spd bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c romstage-y += board_id.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c ramstage-y += mainboard.c diff --git a/src/mainboard/intel/icelake_rvp/bootmode.c b/src/mainboard/intel/icelake_rvp/bootmode.c new file mode 100644 index 0000000..7709f94 --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/bootmode.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> + +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index ea5a1b5..f232478 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -1,11 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi.h> -#include <baseboard/gpio.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <gpio.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -16,14 +13,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_lid_switch(void) -{ - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - return 0; -} diff --git a/src/mainboard/intel/jasperlake_rvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/Makefile.inc index c680b23..f2633ba 100644 --- a/src/mainboard/intel/jasperlake_rvp/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/Makefile.inc @@ -3,14 +3,12 @@ subdirs-y += spd bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c romstage-y += board_id.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += board_id.c diff --git a/src/mainboard/intel/jasperlake_rvp/bootmode.c b/src/mainboard/intel/jasperlake_rvp/bootmode.c new file mode 100644 index 0000000..79fd969 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/bootmode.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> + +#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ + diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index b09a140..f232478 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/gpio.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <gpio.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -15,17 +13,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) -int get_lid_switch(void) -{ - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - return 0; -} - -#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ diff --git a/src/mainboard/intel/kblrvp/Makefile.inc b/src/mainboard/intel/kblrvp/Makefile.inc index 80821eb..29286f7 100644 --- a/src/mainboard/intel/kblrvp/Makefile.inc +++ b/src/mainboard/intel/kblrvp/Makefile.inc @@ -4,13 +4,11 @@ bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += board_id.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += board_id.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c diff --git a/src/mainboard/intel/kblrvp/bootmode.c b/src/mainboard/intel/kblrvp/bootmode.c new file mode 100644 index 0000000..ad3f7fb --- /dev/null +++ b/src/mainboard/intel/kblrvp/bootmode.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" + +int get_lid_switch(void) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + /* Read lid switch state from the EC. */ + return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); + + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + /* Check for dedicated recovery switch first. */ + if (google_chromeec_get_switches() & + EC_SWITCH_DEDICATED_RECOVERY) + return 1; + + /* Otherwise check if the EC has posted the keyboard recovery + * event. */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + } + + return 0; +} diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index a5ea9e9..2c60449 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -3,15 +3,9 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/device.h> -#include <gpio.h> #include <soc/gpio.h> -#include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> -#include "gpio.h" -#include "ec.h" - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -22,33 +16,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_lid_switch(void) -{ - if (CONFIG(EC_GOOGLE_CHROMEEC)) - /* Read lid switch state from the EC. */ - return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); - - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - /* Check for dedicated recovery switch first. */ - if (google_chromeec_get_switches() & - EC_SWITCH_DEDICATED_RECOVERY) - return 1; - - /* Otherwise check if the EC has posted the keyboard recovery - * event. */ - return !!(google_chromeec_get_events_b() & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); - } - - return 0; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index f7ea681..9b083b1 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -4,9 +4,7 @@ bootblock-y += bootblock_mainboard.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c diff --git a/src/mainboard/intel/kunimitsu/bootmode.c b/src/mainboard/intel/kunimitsu/bootmode.c new file mode 100644 index 0000000..f6c6ff6 --- /dev/null +++ b/src/mainboard/intel/kunimitsu/bootmode.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> +#include <soc/gpio.h> +#include "gpio.h" + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 6e8df96..3074262 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -20,12 +20,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/shadowmountain/Makefile.inc b/src/mainboard/intel/shadowmountain/Makefile.inc index 5406547..8b9c811 100644 --- a/src/mainboard/intel/shadowmountain/Makefile.inc +++ b/src/mainboard/intel/shadowmountain/Makefile.inc @@ -1,13 +1,11 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/intel/shadowmountain/bootmode.c b/src/mainboard/intel/shadowmountain/bootmode.c new file mode 100644 index 0000000..2743418 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/bootmode.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <bootmode.h> +#include <gpio.h> + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} diff --git a/src/mainboard/intel/shadowmountain/chromeos.c b/src/mainboard/intel/shadowmountain/chromeos.c index 14f48ec..36232d8 100644 --- a/src/mainboard/intel/shadowmountain/chromeos.c +++ b/src/mainboard/intel/shadowmountain/chromeos.c @@ -17,9 +17,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index 93c9c49..d198737 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -3,14 +3,12 @@ subdirs-y += spd bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c romstage-y += board_id.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/intel/tglrvp/bootmode.c b/src/mainboard/intel/tglrvp/bootmode.c new file mode 100644 index 0000000..79fd969 --- /dev/null +++ b/src/mainboard/intel/tglrvp/bootmode.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> + +#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ + diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index d2877ad..ce2d8b8 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/gpio.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <gpio.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -16,17 +14,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) -int get_lid_switch(void) -{ - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - return 0; -} - -#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ diff --git a/src/mainboard/intel/wtm2/Makefile.inc b/src/mainboard/intel/wtm2/Makefile.inc index 14e7d98..6c4b433 100644 --- a/src/mainboard/intel/wtm2/Makefile.inc +++ b/src/mainboard/intel/wtm2/Makefile.inc @@ -2,9 +2,8 @@ romstage-y += gpio.c -verstage-y += chromeos.c -romstage-y += chromeos.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += pei_data.c ramstage-y += pei_data.c diff --git a/src/mainboard/intel/wtm2/bootmode.c b/src/mainboard/intel/wtm2/bootmode.c new file mode 100644 index 0000000..5e9a299 --- /dev/null +++ b/src/mainboard/intel/wtm2/bootmode.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> + +/* Compile-time settings for recovery mode. */ +#define REC_MODE_SETTING 0 + +int get_recovery_mode_switch(void) +{ + return REC_MODE_SETTING; +} + diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 6b405ad..3d09b6c 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -3,14 +3,10 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/device.h> #include <soc/chromeos.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Compile-time settings for recovery mode. */ -#define REC_MODE_SETTING 0 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -21,11 +17,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_recovery_mode_switch(void) -{ - return REC_MODE_SETTING; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), -- To view, visit https://review.coreboot.org/c/coreboot/+/59018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4ccd31edc5ab6c4bc7890a8de1ae270141d18a7 Gerrit-Change-Number: 59018 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: lib/thread: Switch to using types.h
by Felix Held (Code Review) 08 Nov '21

08 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58990 ) Change subject: lib/thread: Switch to using types.h ...................................................................... lib/thread: Switch to using types.h thread_mutex uses bool. BUG=b:179699789 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Id26b37d3e38852d72fcb6ff07ed578b0879e55dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58990 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Rob Barnes <robbarnes(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/thread.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Rob Barnes: Looks good to me, approved diff --git a/src/include/thread.h b/src/include/thread.h index 62c6283..19b69fa 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -5,7 +5,7 @@ #include <arch/cpu.h> #include <bootstate.h> #include <commonlib/bsd/cb_err.h> -#include <stdint.h> +#include <types.h> struct thread_mutex { bool locked; -- To view, visit https://review.coreboot.org/c/coreboot/+/58990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id26b37d3e38852d72fcb6ff07ed578b0879e55dd Gerrit-Change-Number: 58990 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: console/printk: Add console_mutex
by Rob Barnes (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Raul Rangel, Julius Werner. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58981 ) Change subject: console/printk: Add console_mutex ...................................................................... Patch Set 3: (1 comment) File src/console/printk.c: https://review.coreboot.org/c/coreboot/+/58981/comment/bf3b38ce_dd82cd41 PS3, Line 86: thread_mutex_lock(&console_mutex); Should this be wrapped in an if/else? i.e. do we need to spin_lock and thread_mutex_lock if spin_locks are enabled? -- To view, visit https://review.coreboot.org/c/coreboot/+/58981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5858bb18723f32f6b1e6ef0ed31906d7c79d3fec Gerrit-Change-Number: 58981 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 08 Nov 2021 15:07:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/thread: Remove printk in thread_mutex_lock
by Rob Barnes (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58980 ) Change subject: lib/thread: Remove printk in thread_mutex_lock ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58980/comment/cc2385a1_49807d8d PS2, Line 9: While helpful, it will cause a dead lock with the next CL that adds a Will this dead lock occur when generally using a stopwatch around a printk? -- To view, visit https://review.coreboot.org/c/coreboot/+/58980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a28f9c777fc0fb3bb73dff9e0974aeb6e210bba Gerrit-Change-Number: 58980 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 15:04:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: majolica: Add spaces for EC firmware to enable Type-C adaptor
by Bao Zheng (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Zheng Bao, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59010 ) Change subject: majolica: Add spaces for EC firmware to enable Type-C adaptor ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59010/comment/514514ff_03d215be PS1, Line 7: majolica > Please use the common prefixes: mb/amd/majolica. Done https://review.coreboot.org/c/coreboot/+/59010/comment/78314599_ce7e311c PS1, Line 7: Add spaces for EC firmware to enable Type-C adaptor > FMAP: Increase EC FW space to 148 KB for Type-C adaptor Done File src/mainboard/amd/majolica/Kconfig: https://review.coreboot.org/c/coreboot/+/59010/comment/17cd00f1_dc580b3c PS1, Line 41: 20kByte is > are Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib311e46c8765f17a1af5bc0b00c387268f4cfae5 Gerrit-Change-Number: 59010 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 14:56:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Enable CBFS_PRELOAD
by Paul Fagerburg (Code Review) 08 Nov '21

08 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58961 ) Change subject: soc/amd/cezanne: Enable CBFS_PRELOAD ...................................................................... soc/amd/cezanne: Enable CBFS_PRELOAD The follow up CLs will use CBFS_PRELOAD. The default CBFS_CACHE_SIZE was derived by examining the `cbfstool print` output and summing the files we intend to preload. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I208067e6ceec6ffb602a87bee3bf99a0a75c822d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58961 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index a09e9f9..dbafa8c 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -195,6 +195,7 @@ bool "Loads files from SPI asynchronously" select COOP_MULTITASKING select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + select CBFS_PRELOAD select PAYLOAD_PRELOAD help When enabled, the platform will use the LPC SPI DMA controller to @@ -202,6 +203,10 @@ boot time because the CPUs can be performing useful work while the SPI contents are being preloaded. +config CBFS_CACHE_SIZE + hex + default 0x40000 if CBFS_PRELOAD + config RAMBASE hex default 0x10000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/58961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I208067e6ceec6ffb602a87bee3bf99a0a75c822d Gerrit-Change-Number: 58961 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: spd: Add new LP5 parts and generate SPDs
by Paul Fagerburg (Code Review) 08 Nov '21

08 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58929 ) Change subject: spd: Add new LP5 parts and generate SPDs ...................................................................... spd: Add new LP5 parts and generate SPDs Add the parts below which will be used by the brya variant Vell. Add the parts to memory_parts.json and generate the SPDs using spd_gen. Micron MT62F512M32D2DR-031 WT:B Micron MT62F1G32D4DR-031 WT:B Hynix H9JCNNNCP3MLYR-N6E Generated using: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BUG=b:204284866 TEST=None Change-Id: Ifbcadfb78281b2b78a61a9b61180c421748193a0 Signed-off-by: Reka Norman <rekanorman(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58929 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M spd/lp5/memory_parts.json M spd/lp5/set-0/parts_spd_manifest.generated.txt A spd/lp5/set-0/spd-1.hex A spd/lp5/set-0/spd-2.hex 4 files changed, 99 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json index ef8d9f9..7b3e765 100644 --- a/spd/lp5/memory_parts.json +++ b/spd/lp5/memory_parts.json @@ -1,3 +1,34 @@ { - "parts": [] + "parts": [ + { + "name": "MT62F512M32D2DR-031 WT:B", + "attribs": { + "densityPerDieGb": 8, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 6400 + } + }, + { + "name": "MT62F1G32D4DR-031 WT:B", + "attribs": { + "densityPerDieGb": 8, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 6400 + } + }, + { + "name": "H9JCNNNCP3MLYR-N6E", + "attribs": { + "densityPerDieGb": 8, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 6400 + } + } + ] } diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt index ae22757..31a729d 100644 --- a/spd/lp5/set-0/parts_spd_manifest.generated.txt +++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt @@ -1,3 +1,6 @@ # Generated by: # util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 +MT62F512M32D2DR-031 WT:B,spd-1.hex +MT62F1G32D4DR-031 WT:B,spd-2.hex +H9JCNNNCP3MLYR-N6E,spd-2.hex diff --git a/spd/lp5/set-0/spd-1.hex b/spd/lp5/set-0/spd-1.hex new file mode 100644 index 0000000..6b4ba9f --- /dev/null +++ b/spd/lp5/set-0/spd-1.hex @@ -0,0 +1,32 @@ +23 10 13 0E 15 1A 95 08 00 00 00 00 02 01 00 00 +00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-0/spd-2.hex b/spd/lp5/set-0/spd-2.hex new file mode 100644 index 0000000..92a9046 --- /dev/null +++ b/spd/lp5/set-0/spd-2.hex @@ -0,0 +1,32 @@ +23 10 13 0E 15 1A B5 08 00 00 00 00 0A 01 00 00 +00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/58929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbcadfb78281b2b78a61a9b61180c421748193a0 Gerrit-Change-Number: 58929 Gerrit-PatchSet: 4 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021