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Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )
Change subject: soc/intel/elkhartlake: Introduce Intel PSE
......................................................................
Patch Set 51:
(1 comment)
File src/soc/intel/elkhartlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/55367/comment/582ed5b8_6cd3a557
PS49, Line 127: m_cfg->PchPseEnable = CONFIG(PSE_ENABLE);
> Hi Nico, thanks for your feedback on this. […]
brought me*
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Hello build bot (Jenkins), Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55367
to look at the new patch set (#52).
Change subject: soc/intel/elkhartlake: Introduce Intel PSE
......................................................................
soc/intel/elkhartlake: Introduce Intel PSE
The Intel® Programmable Services Engine (Intel® PSE) is a
dedicated offload engine for IoT functions powered by an ARM
Cortex-M7 microcontroller. It provides independent, low-DMIPS
computing and low-speed I/Os for IoT applications, plus
dedicated services for real-time computing and time-sensitive
synchronization.
The PSE hosts new functions, including remote out-of-band
device management, network proxy, embedded controller lite
and sensor hub.
This CL enables the user to provide the base address of the
PSE FW blob which will then be loaded by the FSP-S onto the
ARM controller. PSE FW will do the initialization work of
PSE controller and it's peripherals. The loading of PSE FW
should have negligible impact on boot time unless PSE
controller could not locate PSE FW and FSP will attempt to
redo PSE FW loading and wait for PSE handshake until it times
out. Once PSE controller locate PSE FW, it will do initialization
concurrently by itself with coreboot booting.
It also adds PSE related FSP-S UPD settings which enables the
setup of peripheral ownership (assigned to the PSE or x86
subsystem) and interrupts. These assignments need to take
place at a given point in the boot process and cannot be
changed later.
To verify if PSE FW is loaded properly, the user could enable
PchPseShellEnabled flag and the log will be printed at PSE UART 2.
For further info please refer to doc #611825 (for HW overview)
and #614110 (for PSE EDS).
Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com>
Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7
---
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/Makefile.inc
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/fsp_params.c
M src/soc/intel/elkhartlake/romstage/fsp_params.c
5 files changed, 173 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/55367/52
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Change subject: soc/intel/elkhartlake: Introduce Intel PSE
......................................................................
Patch Set 51:
(1 comment)
File src/soc/intel/elkhartlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/55367/comment/dde69c31_0df4093d
PS49, Line 127: m_cfg->PchPseEnable = CONFIG(PSE_ENABLE);
> I don't know what OK means on your scale. You outrank me anyway, so […]
Hi Nico, thanks for your feedback on this. Although it always brought be little worries when seeing your review but I do agree your concerns were pretty valid most of the times. And with yours and few other folks reviews (Paul, Filix, Arthur, Angels, Michael) have already made this patch much better than its original patch, once again much appreciated all your hard work and i did learn a few things here 😜
Werner has also put a lot of commitment and hardwork in the back to address this PSE blob mess. It was not easy but the right things have to be done, and I also respect him for that.
Back to this issue, Werner and I were concerned about this, and we are trying to see if a new cbfs API like 'cbfs_check' could be create for this.
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Change subject: lib/thread: Remove printk in thread_mutex_lock
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58980/comment/467b9c0a_3a027178
PS2, Line 9: While helpful, it will cause a dead lock with the next CL that adds a
> Will this dead lock occur when generally using a stopwatch around a printk?
Only if the code is involved in printk, but I think I have a different idea to fix it.
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Change subject: console/printk: Add console_mutex
......................................................................
Patch Set 3:
(1 comment)
File src/console/printk.c:
https://review.coreboot.org/c/coreboot/+/58981/comment/c2e845bc_89acfba7
PS3, Line 86: thread_mutex_lock(&console_mutex);
> Should this be wrapped in an if/else? i.e. […]
I think I might take a different approach. Going to try it out.
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59017 )
Change subject: soc/amd/psp_verstage: Get vb2_context early
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/59017/comment/228ec9e2_bfc566fe
PS1, Line 226: verstage_soc_early_init
> No, I have not seen verstage_soc_early_init fail. […]
Ok good. I'l let khwon@ give the final +2, since I'm not actually sure what implications initializing the context this early has.
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Change subject: soc/intel/elkhartlake: Introduce Intel PSE
......................................................................
Patch Set 51:
(1 comment)
File src/soc/intel/elkhartlake/fsp_params.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132590):
https://review.coreboot.org/c/coreboot/+/55367/comment/8405627c_34903114
PS51, Line 434: if (CONFIG(PSE_ENABLE)) {
braces {} are not necessary for single statement blocks
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Hello build bot (Jenkins), Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55367
to look at the new patch set (#51).
Change subject: soc/intel/elkhartlake: Introduce Intel PSE
......................................................................
soc/intel/elkhartlake: Introduce Intel PSE
The Intel® Programmable Services Engine (Intel® PSE) is a
dedicated offload engine for IoT functions powered by an ARM
Cortex-M7 microcontroller. It provides independent, low-DMIPS
computing and low-speed I/Os for IoT applications, plus
dedicated services for real-time computing and time-sensitive
synchronization.
The PSE hosts new functions, including remote out-of-band
device management, network proxy, embedded controller lite
and sensor hub.
This CL enables the user to provide the base address of the
PSE FW blob which will then be loaded by the FSP-S onto the
ARM controller. PSE FW will do the initialization work of
PSE controller and it's peripherals. The loading of PSE FW
should have negligible impact on boot time unless PSE
controller could not locate PSE FW and FSP will attempt to
redo PSE FW loading and wait for PSE handshake until it times
out. Once PSE controller locate PSE FW, it will do initialization
concurrently by itself with coreboot booting.
It also adds PSE related FSP-S UPD settings which enables the
setup of peripheral ownership (assigned to the PSE or x86
subsystem) and interrupts. These assignments need to take
place at a given point in the boot process and cannot be
changed later.
To verify if PSE FW is loaded properly, the user could enable
PchPseShellEnabled flag and the log will be printed at PSE UART 2.
For further info please refer to doc #611825 (for HW overview)
and #614110 (for PSE EDS).
Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com>
Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7
---
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/Makefile.inc
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/fsp_params.c
M src/soc/intel/elkhartlake/romstage/fsp_params.c
5 files changed, 174 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/55367/51
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Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59017 )
Change subject: soc/amd/psp_verstage: Get vb2_context early
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/59017/comment/f962f2f2_5fd9ea48
PS1, Line 226: verstage_soc_early_init
> Did you actually see verstage_soc_early_init fail? Or did you just noticed the error in the code?
No, I have not seen verstage_soc_early_init fail. I discovered the bug while testing psp verstage during s0i3 resume.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )
Change subject: soc/intel/elkhartlake: Introduce Intel PSE
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Patch Set 50:
(1 comment)
Patchset:
PS50:
> https://review.coreboot. […]
Please ignore, must have slipped from the clipboard.
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