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Change subject: mb/google/dedede/var/bugzzy: Adjust I2C speed
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Patch Set 1: Code-Review+2
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Change subject: mb/google/dedede/var/magolor: Enable ELAN touchscreen for magneto
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Patch Set 2: Code-Review+2
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Change subject: mb/google/dedede/var/bugzzy: Update charger performance control table
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Patch Set 3: Code-Review+2
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Change subject: soc/intel/common: add generic gpio lock mechanism
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Patch Set 4:
(1 comment)
File src/soc/intel/common/block/smm/smihandler.c:
https://review.coreboot.org/c/coreboot/+/58351/comment/1cb0ad8e_dd7d624d
PS1, Line 348: gpio_lock_pad
> I implemented some timestamping to measure the lock timing. […]
I will get rid of the printk in gpio_lock_pad() next and see how much time that pulls out.
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Change subject: soc/amd/{cezanne,picasso}: Stop passing base for fspm.bin
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Patch Set 4: Code-Review+2
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Change subject: pci_mmio_cfg: Always use pci_s_* functions
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Patch Set 5: Code-Review+2
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Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume
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Patch Set 7:
(3 comments)
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/58870/comment/7561a938_487b1c40
PS5, Line 645: config RESUME_PATH_SAME_AS_BOOT
> I'm not sure you should really have this set. […]
+1. Even though we are invoking a small subset of PSP verstage on S0i3 resume, it is not the same as boot path.
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/58870/comment/5970615e_6611d7bc
PS5, Line 230: verstage_mainboard_s0i3_init();
> Is there a good reason the normal verstage_mainboard_early_init() won't work for this? I think it wo […]
I think some additional GPIOs(eg. WLAN_AUX_REST_L) are re-initialized in ramstage. Since ramstage is not involved in S0i3 resume, it just disables those peripherals. Hence this custom GPIO initialization in S0i3 resume sequence. This is another reason selecting RESUME_PATH_SAME_AS_BOOT is not appropriate.
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/58870/comment/8b2b7f4f_93fbdddc
PS6, Line 284: unmap_fch_devices();
Nit: Can be moved inside psp_verstage_s0i3_resume().
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Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume
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Patch Set 7:
(4 comments)
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/58870/comment/ab4c4a6e_8ff7cabf
PS5, Line 645: config RESUME_PATH_SAME_AS_BOOT
I'm not sure you should really have this set. I think this option is really a bit misnamed (and misplaced) at this point... if you look at what it controls, it really just decides whether you run through vboot verification again on resume, and that's not the case for this platform. Maybe we should move this to src/security/vboot/Kconfig and rename it accordingly (or maybe we should just get rid of it and check HAVE_ACPI_RESUME directly in the respective places, there doesn't really seem to be a good reason for the two to be separate).
File src/mainboard/google/guybrush/Kconfig:
https://review.coreboot.org/c/coreboot/+/58870/comment/ef6e2e31_77940a09
PS5, Line 12: select CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME
Unnecessary since it's default y? (Also, it seems like the effect of this won't end up mattering for you anyway...)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/58870/comment/8fd447f9_4e3873d4
PS7, Line 381: PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
This doesn't seem to match the normal GPIO table?
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/58870/comment/f185ea1f_4454b605
PS5, Line 230: verstage_mainboard_s0i3_init();
Is there a good reason the normal verstage_mainboard_early_init() won't work for this? I think it would be better to avoid having to duplicate functionality for this as much as possible.
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