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Change subject: Documentation/releases: Update 4.15 vboot supported boards
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58975/comment/fce53a47_f5fd571d
PS1, Line 9: Update list of boards that support vboot.
Is there a script that can be used for updating this list? I think updating this list by hand takes a lot of effort.
Another idea would be to merge this list with mainboard documentation (doesn't have to be done now, just an idea for the future). I think that would be even better. So people wouldn't have to look at two different places for feature support and also we wouldn't need to maintain board names at two different places.
Again, just a thought for the future :)
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Change subject: soc/intel/common: add generic gpio lock mechanism
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/smm/smihandler.c:
https://review.coreboot.org/c/coreboot/+/58351/comment/bc74b012_efafd476
PS1, Line 348: gpio_lock_pad
> Timing after removing the printk for each gpio locked is MUCH better : […]
may be guard with if (CONFIG(DEBUG_GPIO)) ? to avoid boot time impact ?
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Change subject: soc/intel/common: add generic gpio lock mechanism
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/smm/smihandler.c:
https://review.coreboot.org/c/coreboot/+/58351/comment/8744f271_4640fccf
PS1, Line 348: gpio_lock_pad
> I will get rid of the printk in gpio_lock_pad() next and see how much time that pulls out.
Timing after removing the printk for each gpio locked is MUCH better :
soc_lock_gpios: Locking took 2003544
Shall we remove the printk for each gpio and perhaps just replace it with a single printk to say "Locked gpios" ?
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Hello build bot (Jenkins), Martin Roth, Matt DeVillier, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58854
to look at the new patch set (#28).
Change subject: [WIP] util: Add coreboot Configurator
......................................................................
[WIP] util: Add coreboot Configurator
A simply GUI to change settings in coreboot's CBFS, via the nvramtool utility.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: Ie654f6aca57a792be0c295afc081a95ed4d875d1
---
A util/coreboot-configurator/README.md
A util/coreboot-configurator/contrib/PKGBUILD
A util/coreboot-configurator/contrib/README.md
A util/coreboot-configurator/contrib/debian/changelog
A util/coreboot-configurator/contrib/debian/compat
A util/coreboot-configurator/contrib/debian/control
A util/coreboot-configurator/contrib/debian/files
A util/coreboot-configurator/contrib/debian/rules
A util/coreboot-configurator/contrib/debian/source/format
A util/coreboot-configurator/contrib/flatpak/coreboot-configurator.json
A util/coreboot-configurator/contrib/flatpak/org.coreboot.coreboot-configurator.json
A util/coreboot-configurator/meson.build
A util/coreboot-configurator/meson_options.txt
A util/coreboot-configurator/screenshots/coreboot-configurator.gif
A util/coreboot-configurator/screenshots/coreboot-configurator.png
A util/coreboot-configurator/src/application/aboutwindow.cpp
A util/coreboot-configurator/src/application/aboutwindow.h
A util/coreboot-configurator/src/application/aboutwindow.ui
A util/coreboot-configurator/src/application/categories.yaml
A util/coreboot-configurator/src/application/configuration.cpp
A util/coreboot-configurator/src/application/configuration.h
A util/coreboot-configurator/src/application/corebootconfigurator.cpp
A util/coreboot-configurator/src/application/corebootconfigurator.h
A util/coreboot-configurator/src/application/corebootconfigurator.ui
A util/coreboot-configurator/src/application/images.qrc
A util/coreboot-configurator/src/application/main.cpp
A util/coreboot-configurator/src/application/meson.build
A util/coreboot-configurator/src/application/nvramtoolcli.cpp
A util/coreboot-configurator/src/application/nvramtoolcli.h
A util/coreboot-configurator/src/application/qtyaml.h
A util/coreboot-configurator/src/application/toggle-off.svg
A util/coreboot-configurator/src/application/toggle-on.svg
A util/coreboot-configurator/src/application/toggleswitch.cpp
A util/coreboot-configurator/src/application/toggleswitch.h
A util/coreboot-configurator/src/application/util.h
A util/coreboot-configurator/src/meson.build
A util/coreboot-configurator/src/static/aboutIcon.png
A util/coreboot-configurator/src/static/categories.yaml
A util/coreboot-configurator/src/static/coreboot-configurator.desktop
A util/coreboot-configurator/src/static/coreboot_configurator.svg
A util/coreboot-configurator/src/static/meson.build
A util/coreboot-configurator/src/static/org.coreboot.nvramtool.policy
A util/coreboot-configurator/src/static/org.coreboot.reboot.policy
43 files changed, 3,190 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/58854/28
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Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58870 )
Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume
......................................................................
Patch Set 7:
(5 comments)
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/58870/comment/a7ef8e0d_4c39f748
PS5, Line 645: config RESUME_PATH_SAME_AS_BOOT
> +1. […]
I'm checking CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME and it depends on RESUME_PATH_SAME_AS_BOOT. As pointed out above, resume in the S0i3 context is fundamentally different than the S3 resume. So how about CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME and RESUME_PATH_SAME_AS_BOOT get renamed to CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_S3_RESUME and S3_RESUME_PATH_SAME_AS_BOOT and I remove the checks on these configs from this CL. I think this will mitigate most confusion.
File src/mainboard/google/guybrush/Kconfig:
https://review.coreboot.org/c/coreboot/+/58870/comment/73501b35_95ccd9f2
PS5, Line 12: select CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME
> Unnecessary since it's default y? (Also, it seems like the effect of this won't end up mattering for […]
Not if HAVE_ACPI_RESUME is false. In any case, I plan to remove the check for this config from this CL.
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/58870/comment/8473173b_6a580f70
PS7, Line 381: PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
> This doesn't seem to match the normal GPIO table?
Good catch. The GPIO for GSC_SOC_INT_L moved from GPIO_3 to GPIO_85 in the latest schematic. So the board version will need to be checked before configuring this GPIO.
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/58870/comment/f933c642_c3ac1280
PS5, Line 230: verstage_mainboard_s0i3_init();
> I think some additional GPIOs(eg. WLAN_AUX_REST_L) are re-initialized in ramstage. […]
Yes it can hurt. WLAN_AUX_RESE is asserted in verstage_mainboard_early_init and deasserted in ramstage. So following the same initialization path here will result in a bad state for this GPIO. There may be other examples.
I could move eSPI and TPM gpios out of the early_gpio_table and add verstage_mainboard_tpm_init and verstage_mainboard_espi_init to both the normal verstage boot flow. This removes some of the duplication.
File src/vendorcode/google/chromeos/Kconfig:
https://review.coreboot.org/c/coreboot/+/58870/comment/3c70396c_0d4660c5
PS3, Line 47: depends on TPM2 && RESUME_PATH_SAME_AS_BOOT
> BTW, didn't see this discussion earlier, but as I understand it you're not running through ramstage […]
OK. Let's not depend on RESUME_PATH_SAME_AS_BOOT for this CL.
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Change subject: Documentation/releases: Update 4.15 release notes
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
> Will update the 4.16 right now and we can use that. […]
Oh, I see. Thanks for explaining!
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Change subject: Documentation/releases: Update 4.16 date target
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Please help to review this change.
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Change subject: Documentation/releases: Update 4.16 date target
......................................................................
Documentation/releases: Update 4.16 date target
Change-Id: I6c8327a7cf47217d32359b304b21e806c10dcc62
Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com>
---
M Documentation/releases/coreboot-4.16-relnotes.md
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/59022/1
diff --git a/Documentation/releases/coreboot-4.16-relnotes.md b/Documentation/releases/coreboot-4.16-relnotes.md
index 16a5727..2b17069 100644
--- a/Documentation/releases/coreboot-4.16-relnotes.md
+++ b/Documentation/releases/coreboot-4.16-relnotes.md
@@ -1,7 +1,7 @@
Upcoming release - coreboot 4.16
================================
-The 4.16 release is planned for May 2022.
+The 4.16 release is planned for Februrary, 2022.
Update this document with changes that should be in the release notes.
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Change subject: [WIP] mb/google,intel: Split chromeos.c files
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/intel/kblrvp/bootmode.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132600):
https://review.coreboot.org/c/coreboot/+/59018/comment/2e093167_ebf83c8c
PS4, Line 21: if (google_chromeec_get_switches() &
suspect code indent for conditional statements (16, 16)
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