coreboot-gerrit November 2021

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Change in coreboot[master]: Documentation/releases: Update 4.16 target date and cadence information
by Jason Glenesk (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Felix Singer, Martin Roth, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59022 ) Change subject: Documentation/releases: Update 4.16 target date and cadence information ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59022/comment/8ad74e31_327630c9 PS1, Line 8: > Please mention here the reason, that from now on coreboot will do releases every 3 months Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c8327a7cf47217d32359b304b21e806c10dcc62 Gerrit-Change-Number: 59022 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 20:16:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/releases: Update 4.16 target date and cadence information
by Jason Glenesk (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Martin Roth, Jason Glenesk, Felix Held. Hello Felix Singer, build bot (Jenkins), Martin Roth, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59022 to look at the new patch set (#2). Change subject: Documentation/releases: Update 4.16 target date and cadence information ...................................................................... Documentation/releases: Update 4.16 target date and cadence information Change-Id: I6c8327a7cf47217d32359b304b21e806c10dcc62 Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M Documentation/releases/coreboot-4.16-relnotes.md 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/59022/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c8327a7cf47217d32359b304b21e806c10dcc62 Gerrit-Change-Number: 59022 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Enable Intel FIVR RFI settings
by Tim Wawrzynczak (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Marx Wang, Chen Wisley, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58878 ) Change subject: soc/intel/alderlake: Enable Intel FIVR RFI settings ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37bfef295fcd886d4f01abd40f9467a0791e9e34 Gerrit-Change-Number: 58878 Gerrit-PatchSet: 4 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Marx Wang <marx.wang(a)intel.com> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 08 Nov 2021 20:13:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secbo...
by build bot (Jenkins) (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Ravi kumar. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58545 ) Change subject: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. ...................................................................... Patch Set 5: (1 comment) File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132616): https://review.coreboot.org/c/coreboot/+/58545/comment/242e6cf6_8976fa17 PS5, Line 27: if (soc_modem_carve_out(&start, &end)) that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/58545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 Gerrit-Change-Number: 58545 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Mon, 08 Nov 2021 20:11:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add preload_fspm and preload_fsps
by Tim Wawrzynczak (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Raul Rangel, Andrey Petrov, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58987 ) Change subject: drivers/intel/fsp2_0: Add preload_fspm and preload_fsps ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6 Gerrit-Change-Number: 58987 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 08 Nov 2021 20:10:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Update typeC EC mux port
by Tim Wawrzynczak (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Nick Vaccaro, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59012 ) Change subject: mb/google/brya/var/felwinter: Update typeC EC mux port ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: let's give this a think and see if there's a better way to do this, so we don't have to correctly order the ports in two places (chip ec/google/chromeec -- To view, visit https://review.coreboot.org/c/coreboot/+/59012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19338e162db6145dbeb5830de1a372cf98f779a0 Gerrit-Change-Number: 59012 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 20:08:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware
by Raul Rangel (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56322 ) Change subject: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/common/block/lpc/spi_dma.c: https://review.coreboot.org/c/coreboot/+/56322/comment/d4097018_e5e10d81 PS6, Line 147: + 1 > I either need to `current_block + 1` or `total_blocks - 1`, I figured block 0/100 read like we haven […] reopen if you still have a concern. -- To view, visit https://review.coreboot.org/c/coreboot/+/56322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dd54cab86ad31b135a93d4667df346c60357337 Gerrit-Change-Number: 56322 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 20:04:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/intel/fsp2_0: Added FSP_S component to VBOOT Stage Verifi...
by Raul Rangel (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Amol N Sukerkar. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32155 ) Change subject: src/drivers/intel/fsp2_0: Added FSP_S component to VBOOT Stage Verification. FSP_S component will be verified in RAMSTAGE. ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/32155/comment/adc4f3a5_4e31f3f9 PS2, Line 14: CONFIG_VBOOT_STAGE_VERIFICATION What is CONFIG_VBOOT_STAGE_VERIFICATION? -- To view, visit https://review.coreboot.org/c/coreboot/+/32155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifefad96b54388143fecb56f0402c3b627ae6350d Gerrit-Change-Number: 32155 Gerrit-PatchSet: 2 Gerrit-Owner: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 20:01:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X option
by Raul Rangel (Code Review) 08 Nov '21

08 Nov '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58986 ) Change subject: drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X option ...................................................................... drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X option This option will allow setting the FSP alignment in CBFS. BUG=b:179699789 TEST=Boot with and without the option set and verify -a option was passed. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I4533f6c9d56bea6520aa3aa87dd49f2144a23850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58986 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc 2 files changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index ba93baa..a0e02a8 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -218,6 +218,16 @@ bool depends on !FSP_M_XIP +config FSP_ALIGNMENT_FSP_S + int + help + Sets the CBFS alignment for FSP-S + +config FSP_ALIGNMENT_FSP_M + int + help + Sets the CBFS alignment for FSP-M + config FSP_M_ADDR hex help diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 92ebf24..eaf99d1 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -65,6 +65,9 @@ ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZ4),y) $(FSP_M_CBFS)-compression := LZ4 endif +ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_M),) +$(FSP_M_CBFS)-align := $(CONFIG_FSP_ALIGNMENT_FSP_M) +endif cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(FSP_S_CBFS) $(FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE)) @@ -75,6 +78,9 @@ ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZ4),y) $(FSP_S_CBFS)-compression := LZ4 endif +ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_S),) +$(FSP_S_CBFS)-align := $(CONFIG_FSP_ALIGNMENT_FSP_S) +endif ifeq ($(CONFIG_FSP_FULL_FD),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(DOTCONFIG) -- To view, visit https://review.coreboot.org/c/coreboot/+/58986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4533f6c9d56bea6520aa3aa87dd49f2144a23850 Gerrit-Change-Number: 58986 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/{cezanne,picasso}: Stop passing base for fspm.bin
by Raul Rangel (Code Review) 08 Nov '21

08 Nov '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58985 ) Change subject: soc/amd/{cezanne,picasso}: Stop passing base for fspm.bin ...................................................................... soc/amd/{cezanne,picasso}: Stop passing base for fspm.bin We no longer need to do this since we relocate at runtime. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ibef849d5b3f0290cb7b7c5ff18aabe002bf53344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58985 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/picasso/Makefile.inc 2 files changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 8787441..8db0f6c 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -53,8 +53,6 @@ CPPFLAGS_common += -I$(src)/soc/amd/cezanne/acpi CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne -$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) - MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) # ROMSIG Normally At ROMBASE + 0x20000 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 45e9c80..7db4719 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -281,8 +281,6 @@ apu/amdfw_b-type := raw endif -$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) - cpu_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin) endif # ($(CONFIG_SOC_AMD_PICASSO),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/58985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibef849d5b3f0290cb7b7c5ff18aabe002bf53344 Gerrit-Change-Number: 58985 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021