Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58984 )
Change subject: drivers/intel/fsp2_0: Allow FSP-M to be relocated
......................................................................
drivers/intel/fsp2_0: Allow FSP-M to be relocated
AMD platforms pass in the base address to cbfs tool:
fspm.bin-options: -b $(CONFIG_FSP_M_ADDR)
There is no technical reason not to allow FSP-M to be relocated when
!XIP. By allowing this, we no longer need to pass in the base address
into cbfstool when adding fspm.bin. This enables passing in the
`--alignment` argument to cbfs tool instead. cbfstool currently has a
check that prevents both `-b` and `-a` from being passed in.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I797fb319333c53ad0bbf7340924f7d07dfc7de30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58984
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/commonlib/Makefile.inc
M src/drivers/intel/fsp2_0/util.c
2 files changed, 5 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
index 53975bc..9347f88 100644
--- a/src/commonlib/Makefile.inc
+++ b/src/commonlib/Makefile.inc
@@ -22,6 +22,9 @@
postcar-y += region.c
ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_relocate.c
+ifeq ($(CONFIG_FSP_M_XIP),)
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c
+endif
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c
bootblock-y += cbfs.c
diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c
index 1128013..49934fe 100644
--- a/src/drivers/intel/fsp2_0/util.c
+++ b/src/drivers/intel/fsp2_0/util.c
@@ -163,8 +163,8 @@
if (!dest)
return CB_ERR;
- /* Don't allow FSP-M relocation. */
- if (!fspm_env() && fsp_component_relocate((uintptr_t)dest, dest, output_size) < 0) {
+ /* Don't allow FSP-M relocation when XIP. */
+ if (!fspm_xip() && fsp_component_relocate((uintptr_t)dest, dest, output_size) < 0) {
printk(BIOS_ERR, "Unable to relocate FSP component!\n");
return CB_ERR;
}
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )
Change subject: soc/intel/elkhartlake: Introduce Intel PSE
......................................................................
Patch Set 52:
(1 comment)
Patchset:
PS46:
> Yes, this UPD has already been set to 0 if PSE is disabled. […]
Lean, yes, I got that, but I was talking about having a separate change to fix non-booting devices first which is as easy as adding this Kconfig :-)
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Hello build bot (Jenkins), Martin Roth, Matt DeVillier, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58854
to look at the new patch set (#29).
Change subject: [WIP] util: Add coreboot Configurator
......................................................................
[WIP] util: Add coreboot Configurator
A simply GUI to change settings in coreboot's CBFS, via the nvramtool utility.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: Ie654f6aca57a792be0c295afc081a95ed4d875d1
---
M 3rdparty/blobs
A util/coreboot-configurator/README.md
A util/coreboot-configurator/contrib/PKGBUILD
A util/coreboot-configurator/contrib/README.md
A util/coreboot-configurator/contrib/debian/changelog
A util/coreboot-configurator/contrib/debian/compat
A util/coreboot-configurator/contrib/debian/control
A util/coreboot-configurator/contrib/debian/files
A util/coreboot-configurator/contrib/debian/rules
A util/coreboot-configurator/contrib/debian/source/format
A util/coreboot-configurator/contrib/flatpak/coreboot-configurator.json
A util/coreboot-configurator/contrib/flatpak/org.coreboot.coreboot-configurator.json
A util/coreboot-configurator/meson.build
A util/coreboot-configurator/meson_options.txt
A util/coreboot-configurator/screenshots/coreboot-configurator.gif
A util/coreboot-configurator/screenshots/coreboot-configurator.png
A util/coreboot-configurator/src/application/aboutwindow.cpp
A util/coreboot-configurator/src/application/aboutwindow.h
A util/coreboot-configurator/src/application/aboutwindow.ui
A util/coreboot-configurator/src/application/categories.yaml
A util/coreboot-configurator/src/application/configuration.cpp
A util/coreboot-configurator/src/application/configuration.h
A util/coreboot-configurator/src/application/corebootconfigurator.cpp
A util/coreboot-configurator/src/application/corebootconfigurator.h
A util/coreboot-configurator/src/application/corebootconfigurator.ui
A util/coreboot-configurator/src/application/images.qrc
A util/coreboot-configurator/src/application/main.cpp
A util/coreboot-configurator/src/application/meson.build
A util/coreboot-configurator/src/application/nvramtoolcli.cpp
A util/coreboot-configurator/src/application/nvramtoolcli.h
A util/coreboot-configurator/src/application/qtyaml.h
A util/coreboot-configurator/src/application/toggle-off.svg
A util/coreboot-configurator/src/application/toggle-on.svg
A util/coreboot-configurator/src/application/toggleswitch.cpp
A util/coreboot-configurator/src/application/toggleswitch.h
A util/coreboot-configurator/src/application/util.h
A util/coreboot-configurator/src/meson.build
A util/coreboot-configurator/src/static/aboutIcon.png
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A util/coreboot-configurator/src/static/org.coreboot.nvramtool.policy
A util/coreboot-configurator/src/static/org.coreboot.reboot.policy
44 files changed, 3,210 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/58854/29
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58351 )
Change subject: soc/intel/common: add generic gpio lock mechanism
......................................................................
Patch Set 6:
(3 comments)
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/58351/comment/9c387f91_c3ebc887
PS6, Line 457: cur_list_num
suggestion: you can move this variable declaration to the `for` loop directly. same with 'x' as well.
https://review.coreboot.org/c/coreboot/+/58351/comment/afa6fc92_2dfa7eca
PS6, Line 533: if (status || response) {
: printk(BIOS_ERR, "%s: error status=%x response=%x\n",
: __func__, status, response);
: err_response = (status == -1) ? -1 : response;
: continue;
: }
suggestion: to create a helper function to manage the error case ?
same for line #547?
https://review.coreboot.org/c/coreboot/+/58351/comment/53c61f06_e8e46e2a
PS6, Line 545: = msg.offset +
nit: += 4 ?
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Change subject: soc/intel/common: add generic gpio lock mechanism
......................................................................
soc/intel/common: add generic gpio lock mechanism
For added security, there are some gpios that an SoC will want to lock
once initially configured, such as gpios attached to non-host (x86)
controllers, so that they can't be recofigured at a later point in
time by rogue code.
Likewise, a mainboard may have some gpios connected to secure busses
and/or devices that they want to protect from being changed post
initial configuration.
This change adds a generic gpio locking mechanism that allows the SoC
to export a list of GPIOs to be locked down and allows the mainboard
to export a list of GPIOs that it wants locked down once
initialization is complete.
Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to
enable this feature.
BUG=b:201430600
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify
brya0 boots successfully to kernel.
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14
---
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/include/intelblocks/gpio.h
M src/soc/intel/common/block/smm/Kconfig
M src/soc/intel/common/block/smm/smihandler.c
4 files changed, 164 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/58351/6
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59022 )
Change subject: Documentation/releases: Update 4.16 date target
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59022/comment/3047dd17_fa3a0709
PS1, Line 8:
Please mention here the reason, that from now on coreboot will do releases every 3 months
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Change subject: soc/intel/common: add generic gpio lock mechanism
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/smm/smihandler.c:
https://review.coreboot.org/c/coreboot/+/58351/comment/81025e57_bae09dff
PS1, Line 348: gpio_lock_pad
> may be guard with if (CONFIG(DEBUG_GPIO)) ? to avoid boot time impact ?
Good suggestion, Subrata. I'll add it back in guarded.
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49768 )
Change subject: sc7280: Add CPUCP firmware support
......................................................................
Patch Set 87:
(2 comments)
File src/soc/qualcomm/sc7280/include/soc/cpucp.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132603):
https://review.coreboot.org/c/coreboot/+/49768/comment/6c2ab54d_aa5c6307
PS87, Line 6: #define EPSSTOP_EPSS_TOP (void *)0x18598000
Macros with complex values should be enclosed in parentheses
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132603):
https://review.coreboot.org/c/coreboot/+/49768/comment/9bebaa8e_f5bec739
PS87, Line 7: #define EPSSFAST_BASE_ADDR (void *)0x18580000
Macros with complex values should be enclosed in parentheses
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Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, Karthik Ramasubramanian.
Hello Bora Guvendik, build bot (Jenkins), Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58351
to look at the new patch set (#5).
Change subject: soc/intel/common: add generic gpio lock mechanism
......................................................................
soc/intel/common: add generic gpio lock mechanism
For added security, there are some gpios that an SoC will want to lock
once initially configured, such as gpios attached to non-host (x86)
controllers, so that they can't be recofigured at a later point in
time by rogue code.
Likewise, a mainboard may have some gpios connected to secure busses
and/or devices that they want to protect from being changed post
initial configuration.
This change adds a generic gpio locking mechanism that allows the SoC
to export a list of GPIOs to be locked down and allows the mainboard
to export a list of GPIOs that it wants locked down once
initialization is complete.
Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to
enable this feature.
BUG=b:201430600
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify
brya0 boots successfully to kernel.
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14
---
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/include/intelblocks/gpio.h
M src/soc/intel/common/block/smm/Kconfig
M src/soc/intel/common/block/smm/smihandler.c
4 files changed, 158 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/58351/5
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