Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro.
Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59018
to look at the new patch set (#4).
Change subject: [WIP] mb/google,intel: Split chromeos.c files
......................................................................
[WIP] mb/google,intel: Split chromeos.c files
Move all the low-level GPIO support in bootmode.c files and build
them for all stages. Keep ChromeOS related ACPI and lbtable support
in chromeos.c files and build them only for ramstage.
Change-Id: Ib4ccd31edc5ab6c4bc7890a8de1ae270141d18a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/google/asurada/Makefile.inc
A src/mainboard/google/asurada/bootmode.c
M src/mainboard/google/asurada/chromeos.c
M src/mainboard/google/brya/Makefile.inc
A src/mainboard/google/brya/bootmode.c
M src/mainboard/google/brya/chromeos.c
M src/mainboard/google/cherry/Makefile.inc
A src/mainboard/google/cherry/bootmode.c
M src/mainboard/google/cherry/chromeos.c
M src/mainboard/google/corsola/Makefile.inc
R src/mainboard/google/corsola/bootmode.c
M src/mainboard/google/daisy/Makefile.inc
A src/mainboard/google/daisy/bootmode.c
M src/mainboard/google/daisy/chromeos.c
M src/mainboard/google/dedede/Makefile.inc
A src/mainboard/google/dedede/bootmode.c
M src/mainboard/google/dedede/chromeos.c
M src/mainboard/google/eve/Makefile.inc
A src/mainboard/google/eve/bootmode.c
M src/mainboard/google/eve/chromeos.c
M src/mainboard/google/fizz/Makefile.inc
A src/mainboard/google/fizz/bootmode.c
M src/mainboard/google/fizz/chromeos.c
M src/mainboard/google/foster/Makefile.inc
A src/mainboard/google/foster/bootmode.c
M src/mainboard/google/foster/chromeos.c
M src/mainboard/google/gale/Makefile.inc
A src/mainboard/google/gale/bootmode.c
M src/mainboard/google/gale/chromeos.c
M src/mainboard/google/glados/Makefile.inc
A src/mainboard/google/glados/bootmode.c
M src/mainboard/google/glados/chromeos.c
M src/mainboard/google/gru/Makefile.inc
A src/mainboard/google/gru/bootmode.c
M src/mainboard/google/gru/chromeos.c
M src/mainboard/google/hatch/Makefile.inc
A src/mainboard/google/hatch/bootmode.c
M src/mainboard/google/hatch/chromeos.c
M src/mainboard/google/kahlee/Makefile.inc
A src/mainboard/google/kahlee/bootmode.c
M src/mainboard/google/kahlee/chromeos.c
M src/mainboard/google/kukui/Makefile.inc
A src/mainboard/google/kukui/bootmode.c
M src/mainboard/google/kukui/chromeos.c
M src/mainboard/google/nyan/Makefile.inc
A src/mainboard/google/nyan/bootmode.c
M src/mainboard/google/nyan/chromeos.c
M src/mainboard/google/nyan_big/Makefile.inc
A src/mainboard/google/nyan_big/bootmode.c
M src/mainboard/google/nyan_big/chromeos.c
M src/mainboard/google/nyan_blaze/Makefile.inc
A src/mainboard/google/nyan_blaze/bootmode.c
M src/mainboard/google/nyan_blaze/chromeos.c
M src/mainboard/google/oak/Makefile.inc
A src/mainboard/google/oak/bootmode.c
M src/mainboard/google/oak/chromeos.c
M src/mainboard/google/octopus/Makefile.inc
A src/mainboard/google/octopus/bootmode.c
M src/mainboard/google/octopus/chromeos.c
M src/mainboard/google/peach_pit/Makefile.inc
A src/mainboard/google/peach_pit/bootmode.c
M src/mainboard/google/peach_pit/chromeos.c
M src/mainboard/google/poppy/Makefile.inc
A src/mainboard/google/poppy/bootmode.c
M src/mainboard/google/poppy/chromeos.c
M src/mainboard/google/rambi/Makefile.inc
M src/mainboard/google/rambi/chromeos.c
M src/mainboard/google/reef/Makefile.inc
A src/mainboard/google/reef/bootmode.c
M src/mainboard/google/reef/chromeos.c
M src/mainboard/google/smaug/Makefile.inc
A src/mainboard/google/smaug/bootmode.c
M src/mainboard/google/smaug/chromeos.c
M src/mainboard/google/storm/Makefile.inc
A src/mainboard/google/storm/bootmode.c
M src/mainboard/google/storm/chromeos.c
M src/mainboard/google/trogdor/Makefile.inc
A src/mainboard/google/trogdor/bootmode.c
M src/mainboard/google/trogdor/chromeos.c
M src/mainboard/google/veyron/Makefile.inc
A src/mainboard/google/veyron/bootmode.c
M src/mainboard/google/veyron/chromeos.c
M src/mainboard/google/veyron_mickey/Makefile.inc
A src/mainboard/google/veyron_mickey/bootmode.c
M src/mainboard/google/veyron_mickey/chromeos.c
M src/mainboard/google/veyron_rialto/Makefile.inc
A src/mainboard/google/veyron_rialto/bootmode.c
M src/mainboard/google/veyron_rialto/chromeos.c
M src/mainboard/google/volteer/Makefile.inc
A src/mainboard/google/volteer/bootmode.c
M src/mainboard/google/volteer/chromeos.c
M src/mainboard/google/zork/Makefile.inc
A src/mainboard/google/zork/bootmode.c
M src/mainboard/google/zork/chromeos.c
M src/mainboard/intel/adlrvp/Makefile.inc
A src/mainboard/intel/adlrvp/bootmode.c
M src/mainboard/intel/adlrvp/chromeos.c
M src/mainboard/intel/coffeelake_rvp/Makefile.inc
A src/mainboard/intel/coffeelake_rvp/bootmode.c
M src/mainboard/intel/coffeelake_rvp/chromeos.c
M src/mainboard/intel/glkrvp/Makefile.inc
A src/mainboard/intel/glkrvp/bootmode.c
M src/mainboard/intel/glkrvp/chromeos.c
M src/mainboard/intel/icelake_rvp/Makefile.inc
A src/mainboard/intel/icelake_rvp/bootmode.c
M src/mainboard/intel/icelake_rvp/chromeos.c
M src/mainboard/intel/jasperlake_rvp/Makefile.inc
A src/mainboard/intel/jasperlake_rvp/bootmode.c
M src/mainboard/intel/jasperlake_rvp/chromeos.c
M src/mainboard/intel/kblrvp/Makefile.inc
A src/mainboard/intel/kblrvp/bootmode.c
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/kunimitsu/Makefile.inc
A src/mainboard/intel/kunimitsu/bootmode.c
M src/mainboard/intel/kunimitsu/chromeos.c
M src/mainboard/intel/shadowmountain/Makefile.inc
A src/mainboard/intel/shadowmountain/bootmode.c
M src/mainboard/intel/shadowmountain/chromeos.c
M src/mainboard/intel/tglrvp/Makefile.inc
A src/mainboard/intel/tglrvp/bootmode.c
M src/mainboard/intel/tglrvp/chromeos.c
M src/mainboard/intel/wtm2/Makefile.inc
A src/mainboard/intel/wtm2/bootmode.c
M src/mainboard/intel/wtm2/chromeos.c
124 files changed, 991 insertions(+), 848 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/59018/4
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib4ccd31edc5ab6c4bc7890a8de1ae270141d18a7
Gerrit-Change-Number: 59018
Gerrit-PatchSet: 4
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58734 )
Change subject: mb/google/dedede/var/galtic: update Wifi SAR for convertibles
......................................................................
Patch Set 6:
(3 comments)
File src/mainboard/google/dedede/variants/galtic/variant.c:
https://review.coreboot.org/c/coreboot/+/58734/comment/b1c36fb7_7dacc2ca
PS6, Line 23: return "wifi_sar-galtic.hex";
> If WIFI_SAR_CBFS_DEFAULT_FILENAME is wifi_sar-galtic. […]
+1
https://review.coreboot.org/c/coreboot/+/58734/comment/4e67e60f_50751b76
PS6, Line 27: galith
> should be gallop? Thanks.
I dont see a specific SAR file for Gallop.
https://review.coreboot.org/c/coreboot/+/58734/comment/6e960f40_e812f800
PS6, Line 32: return "WIFI_SAR_CBFS_DEFAULT_FILENAME";
> Where is the CL for new CONFIG_WIFI_SAR_CBFS_FILEPATH? Thanks.
https://chromium-review.googlesource.com/c/chromiumos/overlays/chromiumos-o…
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58926 )
Change subject: soc/amd/common/block: Add spi_hw mutex
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/spi/fch_spi_ctrl.c:
https://review.coreboot.org/c/coreboot/+/58926/comment/c8f4050c_c76c56ee
PS2, Line 147: thread_mutex_lock
So one unfortunate thing is that we can only transfer ~60 bytes pre transaction, so we lock and unlock the mutex a bunch of times when writing to the SPI ROM. This does cause the printk in thread_mutex_lock to spam a bunch during `elog init`.
There is a .claim_bus and .free_bus callback, but they get called before and after xfer_vectors, so it's not different. Ideally a .claim_bus would get called once, then all the transfers, then release, but that is a pretty big change...
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Change subject: drivers/intel/fsp2_0: Allow FSP-M to be relocated
......................................................................
Patch Set 4: Code-Review+2
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Change subject: [WIP] mb/google,intel: Split chromeos.c files
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/intel/kblrvp/bootmode.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132599):
https://review.coreboot.org/c/coreboot/+/59018/comment/58d4a80b_2de0ea49
PS3, Line 21: if (google_chromeec_get_switches() &
suspect code indent for conditional statements (16, 16)
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59018
to look at the new patch set (#3).
Change subject: [WIP] mb/google,intel: Split chromeos.c files
......................................................................
[WIP] mb/google,intel: Split chromeos.c files
Move all the low-level GPIO support in bootmode.c files and build
them for all stages. Keep ChromeOS related ACPI and lbtable support
in chromeos.c files and build them only for ramstage.
Change-Id: Ib4ccd31edc5ab6c4bc7890a8de1ae270141d18a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/google/asurada/Makefile.inc
A src/mainboard/google/asurada/bootmode.c
M src/mainboard/google/asurada/chromeos.c
M src/mainboard/google/brya/Makefile.inc
A src/mainboard/google/brya/bootmode.c
M src/mainboard/google/brya/chromeos.c
M src/mainboard/google/cherry/Makefile.inc
A src/mainboard/google/cherry/bootmode.c
M src/mainboard/google/cherry/chromeos.c
M src/mainboard/google/corsola/Makefile.inc
R src/mainboard/google/corsola/bootmode.c
M src/mainboard/google/daisy/Makefile.inc
A src/mainboard/google/daisy/bootmode.c
M src/mainboard/google/daisy/chromeos.c
M src/mainboard/google/dedede/Makefile.inc
A src/mainboard/google/dedede/bootmode.c
M src/mainboard/google/dedede/chromeos.c
M src/mainboard/google/eve/Makefile.inc
A src/mainboard/google/eve/bootmode.c
M src/mainboard/google/eve/chromeos.c
M src/mainboard/google/fizz/Makefile.inc
A src/mainboard/google/fizz/bootmode.c
M src/mainboard/google/fizz/chromeos.c
M src/mainboard/google/foster/Makefile.inc
A src/mainboard/google/foster/bootmode.c
M src/mainboard/google/foster/chromeos.c
M src/mainboard/google/gale/Makefile.inc
A src/mainboard/google/gale/bootmode.c
M src/mainboard/google/gale/chromeos.c
M src/mainboard/google/glados/Makefile.inc
A src/mainboard/google/glados/bootmode.c
M src/mainboard/google/glados/chromeos.c
M src/mainboard/google/gru/Makefile.inc
A src/mainboard/google/gru/bootmode.c
M src/mainboard/google/gru/chromeos.c
M src/mainboard/google/hatch/Makefile.inc
A src/mainboard/google/hatch/bootmode.c
M src/mainboard/google/hatch/chromeos.c
M src/mainboard/google/kahlee/Makefile.inc
A src/mainboard/google/kahlee/bootmode.c
M src/mainboard/google/kahlee/chromeos.c
M src/mainboard/google/kukui/Makefile.inc
A src/mainboard/google/kukui/bootmode.c
M src/mainboard/google/kukui/chromeos.c
M src/mainboard/google/nyan/Makefile.inc
A src/mainboard/google/nyan/bootmode.c
M src/mainboard/google/nyan/chromeos.c
M src/mainboard/google/nyan_big/Makefile.inc
A src/mainboard/google/nyan_big/bootmode.c
M src/mainboard/google/nyan_big/chromeos.c
M src/mainboard/google/nyan_blaze/Makefile.inc
A src/mainboard/google/nyan_blaze/bootmode.c
M src/mainboard/google/nyan_blaze/chromeos.c
M src/mainboard/google/oak/Makefile.inc
A src/mainboard/google/oak/bootmode.c
M src/mainboard/google/oak/chromeos.c
M src/mainboard/google/octopus/Makefile.inc
A src/mainboard/google/octopus/bootmode.c
M src/mainboard/google/octopus/chromeos.c
M src/mainboard/google/peach_pit/Makefile.inc
A src/mainboard/google/peach_pit/bootmode.c
M src/mainboard/google/peach_pit/chromeos.c
M src/mainboard/google/poppy/Makefile.inc
A src/mainboard/google/poppy/bootmode.c
M src/mainboard/google/poppy/chromeos.c
M src/mainboard/google/rambi/Makefile.inc
A src/mainboard/google/rambi/bootmode.c
M src/mainboard/google/rambi/chromeos.c
M src/mainboard/google/reef/Makefile.inc
A src/mainboard/google/reef/bootmode.c
M src/mainboard/google/reef/chromeos.c
M src/mainboard/google/smaug/Makefile.inc
A src/mainboard/google/smaug/bootmode.c
M src/mainboard/google/smaug/chromeos.c
M src/mainboard/google/storm/Makefile.inc
A src/mainboard/google/storm/bootmode.c
M src/mainboard/google/storm/chromeos.c
M src/mainboard/google/trogdor/Makefile.inc
A src/mainboard/google/trogdor/bootmode.c
M src/mainboard/google/trogdor/chromeos.c
M src/mainboard/google/veyron/Makefile.inc
A src/mainboard/google/veyron/bootmode.c
M src/mainboard/google/veyron/chromeos.c
M src/mainboard/google/veyron_mickey/Makefile.inc
A src/mainboard/google/veyron_mickey/bootmode.c
M src/mainboard/google/veyron_mickey/chromeos.c
M src/mainboard/google/veyron_rialto/Makefile.inc
A src/mainboard/google/veyron_rialto/bootmode.c
M src/mainboard/google/veyron_rialto/chromeos.c
M src/mainboard/google/volteer/Makefile.inc
A src/mainboard/google/volteer/bootmode.c
M src/mainboard/google/volteer/chromeos.c
M src/mainboard/google/zork/Makefile.inc
A src/mainboard/google/zork/bootmode.c
M src/mainboard/google/zork/chromeos.c
M src/mainboard/intel/adlrvp/Makefile.inc
A src/mainboard/intel/adlrvp/bootmode.c
M src/mainboard/intel/adlrvp/chromeos.c
M src/mainboard/intel/coffeelake_rvp/Makefile.inc
A src/mainboard/intel/coffeelake_rvp/bootmode.c
M src/mainboard/intel/coffeelake_rvp/chromeos.c
M src/mainboard/intel/glkrvp/Makefile.inc
A src/mainboard/intel/glkrvp/bootmode.c
M src/mainboard/intel/glkrvp/chromeos.c
M src/mainboard/intel/icelake_rvp/Makefile.inc
A src/mainboard/intel/icelake_rvp/bootmode.c
M src/mainboard/intel/icelake_rvp/chromeos.c
M src/mainboard/intel/jasperlake_rvp/Makefile.inc
A src/mainboard/intel/jasperlake_rvp/bootmode.c
M src/mainboard/intel/jasperlake_rvp/chromeos.c
M src/mainboard/intel/kblrvp/Makefile.inc
A src/mainboard/intel/kblrvp/bootmode.c
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/kunimitsu/Makefile.inc
A src/mainboard/intel/kunimitsu/bootmode.c
M src/mainboard/intel/kunimitsu/chromeos.c
M src/mainboard/intel/shadowmountain/Makefile.inc
A src/mainboard/intel/shadowmountain/bootmode.c
M src/mainboard/intel/shadowmountain/chromeos.c
M src/mainboard/intel/tglrvp/Makefile.inc
A src/mainboard/intel/tglrvp/bootmode.c
M src/mainboard/intel/tglrvp/chromeos.c
M src/mainboard/intel/wtm2/Makefile.inc
A src/mainboard/intel/wtm2/bootmode.c
M src/mainboard/intel/wtm2/chromeos.c
125 files changed, 1,010 insertions(+), 849 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/59018/3
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Gerrit-Change-Number: 59018
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Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58974 )
Change subject: Documentation/releases: Update 4.15 release notes
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I would do that in this patch since it is announced here. […]
Will update the 4.16 right now and we can use that. There was some talk about increasing the cadence to align to a tool cadence.
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Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59021 )
Change subject: arch/x86/smp/spinlock: Fix threading when !STAGE_HAS_SPINLOCKS
......................................................................
arch/x86/smp/spinlock: Fix threading when !STAGE_HAS_SPINLOCKS
Cooperative multitasking has previously only been used in ramstage. When
running threads in romstage it was observed that two threads could be
trying to write to the serial console. This doesn't happen in ramstage
because when holding a spin lock, threading gets disabled. We need to do
the same thing in romstage. We don't actually need spin locks in
romstage, but we still need to disable multitasking.
One alternative is adding a thread_mutex everywhere a spinlock is
defined, but that seems excessive.
BUG=b:179699789
TEST=Boot guybrush to OS and verify printk is not intermingled in
romstage.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Iea621fcdad8f0367acce4f70be42a4e9a68da938
---
M src/arch/x86/include/arch/smp/spinlock.h
1 file changed, 10 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/59021/1
diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h
index 19e9129..6ba92dd 100644
--- a/src/arch/x86/include/arch/smp/spinlock.h
+++ b/src/arch/x86/include/arch/smp/spinlock.h
@@ -17,8 +17,6 @@
#define STAGE_HAS_SPINLOCKS !ENV_ROMSTAGE_OR_BEFORE
-#if STAGE_HAS_SPINLOCKS
-
#define DECLARE_SPIN_LOCK(x) \
static spinlock_t x = SPIN_LOCK_UNLOCKED;
@@ -42,9 +40,11 @@
static __always_inline void spin_lock(spinlock_t *lock)
{
- __asm__ __volatile__(
- spin_lock_string
- : "=m" (lock->lock) : : "memory");
+ if (STAGE_HAS_SPINLOCKS) {
+ __asm__ __volatile__(
+ spin_lock_string
+ : "=m" (lock->lock) : : "memory");
+ }
/* Switching contexts while holding a spinlock will lead to deadlocks */
thread_coop_disable();
@@ -55,17 +55,11 @@
{
thread_coop_enable();
- __asm__ __volatile__(
- spin_unlock_string
- : "=m" (lock->lock) : : "memory");
+ if (STAGE_HAS_SPINLOCKS) {
+ __asm__ __volatile__(
+ spin_unlock_string
+ : "=m" (lock->lock) : : "memory");
+ }
}
-#else
-
-#define DECLARE_SPIN_LOCK(x)
-#define spin_lock(lock) do {} while (0)
-#define spin_unlock(lock) do {} while (0)
-
-#endif
-
#endif /* ARCH_SMP_SPINLOCK_H */
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