coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/corsola: Configure eMMC and SD Card
by Rex-BC Chen (Code Review) 15 Nov '21

15 Nov '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59293 ) Change subject: mb/google/corsola: Configure eMMC and SD Card ...................................................................... mb/google/corsola: Configure eMMC and SD Card The Corsola reference design has both eMMC and SD Card interfaces so we have to configure both in RAM stage. TEST=boot kernel from eMMC and SDCard ok BUG=b:202871018 Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Change-Id: I0fa8712eb61685a305dc5dd49cc2e55f1f0eecd4 --- M src/mainboard/google/corsola/mainboard.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/59293/1 diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index 195ce67..b13eb15 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -1,10 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include <soc/msdc.h> #include <soc/usb.h> static void mainboard_init(struct device *dev) { + mtk_msdc_configure_emmc(); + mtk_msdc_configure_sdcard(); setup_usb_host(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/59293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fa8712eb61685a305dc5dd49cc2e55f1f0eecd4 Gerrit-Change-Number: 59293 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Configure eMMC and SD Card
by Rex-BC Chen (Code Review) 15 Nov '21

15 Nov '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59292 ) Change subject: soc/mediatek/mt8186: Configure eMMC and SD Card ...................................................................... soc/mediatek/mt8186: Configure eMMC and SD Card The Corsola reference design has both eMMC and SD Card interfaces so we have to configure both in RAM stage. TEST=build pass BUG=b:202871018 Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293 --- M src/mainboard/google/corsola/Kconfig M src/soc/mediatek/common/include/soc/msdc.h M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/msdc.c 4 files changed, 112 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/59292/1 diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index f8906d6..cb6c968 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -14,6 +14,8 @@ select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH select SPI_FLASH_INCLUDE_ALL_DRIVERS + select COMMONLIB_STORAGE + select COMMONLIB_STORAGE_MMC config MAINBOARD_DIR string diff --git a/src/soc/mediatek/common/include/soc/msdc.h b/src/soc/mediatek/common/include/soc/msdc.h index 6208b72..26bb25f 100644 --- a/src/soc/mediatek/common/include/soc/msdc.h +++ b/src/soc/mediatek/common/include/soc/msdc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __MSDC_H_ -#define __MSDC_H_ +#ifndef SOC_MEDIATEK_COMMON_MSDC_H +#define SOC_MEDIATEK_COMMON_MSDC_H #include <commonlib/sd_mmc_ctrlr.h> @@ -165,5 +165,7 @@ #define msdc_error(format...) printk(BIOS_ERR, "ERROR: " format) int mtk_emmc_early_init(void *base, void *top_base); +void mtk_msdc_configure_emmc(void); +void mtk_msdc_configure_sdcard(void); -#endif // MTK_MMC_H_ +#endif /* SOC_MEDIATEK_COMMON_MSDC_H */ \ No newline at end of file diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 7d6d2ff..cb472ce 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -38,6 +38,7 @@ ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c ramstage-y += ../common/timer.c timer.c diff --git a/src/soc/mediatek/mt8186/msdc.c b/src/soc/mediatek/mt8186/msdc.c new file mode 100644 index 0000000..f1c2004 --- /dev/null +++ b/src/soc/mediatek/mt8186/msdc.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.7 + */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <soc/regulator.h> +#include <soc/msdc.h> + +DEFINE_BITFIELD(MSDC0_DRV, 29, 0) +DEFINE_BITFIELD(MSDC1_DRV, 23, 6) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_0, 18, 16) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_1, 22, 20) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_2, 26, 24) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_3, 30, 28) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_0, 2, 0) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_1, 6, 4) + +#define MSDC0_BASE 0x11230000 +#define MSDC0_TOP_BASE 0x11cd0000 + +#define MSDC0_DRV_VALUE 0x1b6db6db +#define MSDC1_DRV_VALUE 0x1b6db +#define MSDC1_GPIO_MODE0_VALUE 0x1 +#define MSDC1_GPIO_MODE1_VALUE 0x1 + +enum { + MSDC1_GPIO_MODE0_BASE = 0x100053a0, + MSDC1_GPIO_MODE1_BASE = 0x100053b0, +}; + +void mtk_msdc_configure_emmc(void) +{ + void *gpio_base = (void *)IOCFG_LT_BASE; + int i; + + const gpio_t emmc_pu_pin[] = { + GPIO(MSDC0_DAT0), GPIO(MSDC0_DAT1), + GPIO(MSDC0_DAT2), GPIO(MSDC0_DAT3), + GPIO(MSDC0_DAT4), GPIO(MSDC0_DAT5), + GPIO(MSDC0_DAT6), GPIO(MSDC0_DAT7), + GPIO(MSDC0_CMD), GPIO(MSDC0_RSTB), + }; + + const gpio_t emmc_pd_pin[] = { + GPIO(MSDC0_DSL), GPIO(MSDC0_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) + gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) + gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set eMMC cmd/dat/clk pins driving to 8mA */ + SET32_BITFIELDS(gpio_base, MSDC0_DRV, MSDC0_DRV_VALUE); +} + +void mtk_msdc_configure_sdcard(void) +{ + void *gpio_base = (void *)IOCFG_LB_BASE; + void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; + void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; + int i; + + const gpio_t sdcard_pu_pin[] = { + GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), + GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), + GPIO(MSDC1_CMD), + }; + + const gpio_t sdcard_pd_pin[] = { + GPIO(MSDC1_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) + gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) + gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set sdcard cmd/dat/clk pins driving to 8mA */ + SET32_BITFIELDS(gpio_base, MSDC1_DRV, MSDC1_DRV_VALUE); + + /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ + SET32_BITFIELDS(gpio_mode0_base, + MSDC1_GPIO_MODE0_0, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_1, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_2, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_3, MSDC1_GPIO_MODE0_VALUE); + + /* set sdcard dat1 pin to msdc1 mode */ + SET32_BITFIELDS(gpio_mode1_base, + MSDC1_GPIO_MODE1_0, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_1, MSDC1_GPIO_MODE1_VALUE); + + /* enable SDCard power */ + mainboard_set_regulator_vol(MTK_REGULATOR_VMCH, 3300000); + mainboard_set_regulator_vol(MTK_REGULATOR_VMC, 3300000); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293 Gerrit-Change-Number: 59292 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/../thermal: Refactor PCH Thermal Configuration common API
by EricR Lai (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Refactor PCH Thermal Configuration common API ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59209/comment/ee5fdb06_3c944329 PS6, Line 10: /* Fix compilation issue when SoC doesn't have PCH_DEVFN_THERMAL defined */ > Yes. okay, I see 👍 -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 04:52:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Refactor PCH Thermal Configuration common API
by Subrata Banik (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Refactor PCH Thermal Configuration common API ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59209/comment/33bdb2dd_6488d3ea PS6, Line 10: /* Fix compilation issue when SoC doesn't have PCH_DEVFN_THERMAL defined */ > oh.. […] Yes. -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 04:51:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Refactor PCH Thermal Configuration common API
by EricR Lai (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Refactor PCH Thermal Configuration common API ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59209/comment/ea7498de_582bc770 PS6, Line 10: /* Fix compilation issue when SoC doesn't have PCH_DEVFN_THERMAL defined */ > > Maybe we should add back to old soc? Should not be too many. […] oh.. is that different than SA_DEV_SLOT_DPTF? -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 04:49:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Create vell variant
by Tim Wawrzynczak (Code Review) 15 Nov '21

15 Nov '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59242 ) Change subject: mb/google/brya: Create vell variant ...................................................................... mb/google/brya: Create vell variant Create the vell variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:205908918 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_VELL Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Change-Id: Ide8ba1c0dd9b5d9ad90556053abf2a597136a10c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59242 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/vell/include/variant/ec.h A src/mainboard/google/brya/variants/vell/include/variant/gpio.h A src/mainboard/google/brya/variants/vell/memory/Makefile.inc A src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/vell/overridetree.cb 8 files changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 850a78c..70729c9 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -103,6 +103,7 @@ default "Taeko" if BOARD_GOOGLE_TAEKO default "Felwinter" if BOARD_GOOGLE_FELWINTER default "Anahera" if BOARD_GOOGLE_ANAHERA + default "Vell" if BOARD_GOOGLE_VELL config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -114,6 +115,7 @@ default "taeko" if BOARD_GOOGLE_TAEKO default "felwinter" if BOARD_GOOGLE_FELWINTER default "anahera" if BOARD_GOOGLE_ANAHERA + default "vell" if BOARD_GOOGLE_VELL config DIMM_SPD_SIZE default 512 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 8d58fa5..bd8cf6f 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -67,3 +67,7 @@ select DRIVERS_GENESYSLOGIC_GL9763E select DRIVERS_GFX_GENERIC select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + +config BOARD_GOOGLE_VELL + bool "-> Vell" + select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/vell/include/variant/ec.h b/src/mainboard/google/brya/variants/vell/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/vell/include/variant/gpio.h b/src/mainboard/google/brya/variants/vell/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/vell/memory/Makefile.inc b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc new file mode 100644 index 0000000..6751a42 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide8ba1c0dd9b5d9ad90556053abf2a597136a10c Gerrit-Change-Number: 59242 Gerrit-PatchSet: 3 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/../thermal: Refactor PCH Thermal Configuration common API
by Subrata Banik (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Refactor PCH Thermal Configuration common API ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59209/comment/31782fdd_320fa5f3 PS6, Line 10: /* Fix compilation issue when SoC doesn't have PCH_DEVFN_THERMAL defined */ > Maybe we should add back to old soc? Should not be too many. @Eric, I don't think I understood your feedback well but the compilation issue as highlighted here is seen with latest SoC since TGL as there is no thermal device in PCI tree and its located behind PMC register. Hence, there is no `PCH_DEVFN_THERMAL` in pci_devs.h under SoC directory for newer SoC to resolve the error. -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 04:44:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add config option for S3 ACPI
by Tim Wawrzynczak (Code Review) 15 Nov '21

15 Nov '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59024 ) Change subject: soc/intel/tigerlake: Add config option for S3 ACPI ...................................................................... soc/intel/tigerlake: Add config option for S3 ACPI Add Kconfig option `SOC_INTEL_TIGERLAKE_S3` which will adjust the ACPI to not offer D3Cold when using S3. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ieb1cc3d6a03cb452ff38ae393a993e881d9b5ff4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59024 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/tcss.asl M src/soc/intel/tigerlake/acpi/tcss_dma.asl M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl M src/soc/intel/tigerlake/acpi/tcss_xhci.asl 5 files changed, 189 insertions(+), 126 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 91f3316..a7b3ae4 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -187,6 +187,12 @@ int default 6 +config SOC_INTEL_TIGERLAKE_S3 + bool + default n + help + Select if using S3 instead of S0ix to disable D3Cold + config SOC_INTEL_UART_DEV_MAX int default 3 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index cdbf0cc..1d58bfb 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -41,6 +41,12 @@ Scope (\_SB) { +#if CONFIG(SOC_INTEL_TIGERLAKE_S3) + Name (S0IX, 0) +#else + Name (S0IX, 1) +#endif + /* Device base address */ Method (BASE, 1) { @@ -673,116 +679,118 @@ } } - Method (TCON, 0) - { - /* Reset IOM D3 cold bit if it is in D3 cold now. */ - If (TD3C == 1) /* It was in D3 cold before. */ + If (S0IX == 1) { + Method (TCON, 0) { - /* Reset IOM D3 cold bit. */ - TD3C = 0 /* Request IOM for D3 cold exit sequence. */ - Local0 = 0 /* Time check counter variable */ - /* Wait for ack, the maximum wait time for the ack is 100 msec. */ - While ((TACK != 0) && (Local0 < TCSS_IOM_ACK_TIMEOUT_IN_MS)) { - /* - * Wait in this loop until TACK becomes 0 with timeout - * TCSS_IOM_ACK_TIMEOUT_IN_MS by default. - */ - Sleep (1) /* Delay of 1ms. */ - Local0++ - } - - If (Local0 == TCSS_IOM_ACK_TIMEOUT_IN_MS) { - Printf("Error: Timeout occurred.") - } - Else + /* Reset IOM D3 cold bit if it is in D3 cold now. */ + If (TD3C == 1) /* It was in D3 cold before. */ { - /* - * Program IOP MCTP Drop (TCSS_IN_D3) after D3 cold exit and - * acknowledgement by IOM. - */ - TCD3 = 0 - /* - * If the TCSS Deven is cleared by BIOS Mailbox request, then - * restore to previously saved value of TCSS DEVNE. - */ - Local0 = 0 - While (\_SB.PCI0.TXHC.VDID == 0xFFFFFFFF) { - If (DSGS () == 1) { - DSCR (0) - } + /* Reset IOM D3 cold bit. */ + TD3C = 0 /* Request IOM for D3 cold exit sequence. */ + Local0 = 0 /* Time check counter variable */ + /* Wait for ack, the maximum wait time for the ack is 100 msec. */ + While ((TACK != 0) && (Local0 < TCSS_IOM_ACK_TIMEOUT_IN_MS)) { + /* + * Wait in this loop until TACK becomes 0 with timeout + * TCSS_IOM_ACK_TIMEOUT_IN_MS by default. + */ + Sleep (1) /* Delay of 1ms. */ Local0++ - If (Local0 == 5) { - Printf("pCode mailbox command failed.") - Break + } + + If (Local0 == TCSS_IOM_ACK_TIMEOUT_IN_MS) { + Printf("Error: Timeout occurred.") + } + Else + { + /* + * Program IOP MCTP Drop (TCSS_IN_D3) after D3 cold exit and + * acknowledgement by IOM. + */ + TCD3 = 0 + /* + * If the TCSS Deven is cleared by BIOS Mailbox request, then + * restore to previously saved value of TCSS DEVNE. + */ + Local0 = 0 + While (\_SB.PCI0.TXHC.VDID == 0xFFFFFFFF) { + If (DSGS () == 1) { + DSCR (0) + } + Local0++ + If (Local0 == 5) { + Printf("pCode mailbox command failed.") + Break + } } } } - } - Else { - Printf("Drop TCON due to it is already exit D3 cold.") - } - } - - Method (TCOF, 0) - { - If ((\_SB.PCI0.TXHC.SD3C != 0) || (\_SB.PCI0.TDM0.SD3C != 0) - || (\_SB.PCI0.TDM1.SD3C != 0)) - { - Printf("Skip D3C entry.") - Return - } - - /* - * If the TCSS Deven in normal state, then Save current TCSS DEVEN value and - * clear it. - */ - Local0 = 0 - While (\_SB.PCI0.TXHC.VDID != 0xFFFFFFFF) { - If (DSGS () == 0) { - DSCR (1) - } - Local0++ - If (Local0 == 5) { - Printf("pCode mailbox command failed.") - Break + Else { + Printf("Drop TCON due to it is already exit D3 cold.") } } - /* - * Program IOM MCTP Drop (TCSS_IN_D3) in D3Cold entry before entering D3 cold. - */ - TCD3 = 1 - - /* Request IOM for D3 cold entry sequence. */ - TD3C = 1 - } - - PowerResource (D3C, 5, 0) - { - /* - * Variable to save power state - * 1 - TC Cold request cleared. - * 0 - TC Cold request sent. - */ - Name (STAT, 0x1) - - Method (_STA, 0) + Method (TCOF, 0) { - Return (STAT) + If ((\_SB.PCI0.TXHC.SD3C != 0) || (\_SB.PCI0.TDM0.SD3C != 0) + || (\_SB.PCI0.TDM1.SD3C != 0)) + { + Printf("Skip D3C entry.") + Return + } + + /* + * If the TCSS Deven in normal state, then Save current TCSS DEVEN value and + * clear it. + */ + Local0 = 0 + While (\_SB.PCI0.TXHC.VDID != 0xFFFFFFFF) { + If (DSGS () == 0) { + DSCR (1) + } + Local0++ + If (Local0 == 5) { + Printf("pCode mailbox command failed.") + Break + } + } + + /* + * Program IOM MCTP Drop (TCSS_IN_D3) in D3Cold entry before entering D3 cold. + */ + TCD3 = 1 + + /* Request IOM for D3 cold entry sequence. */ + TD3C = 1 } - Method (_ON, 0) + PowerResource (D3C, 5, 0) { - \_SB.PCI0.TCON() - STAT = 1 - } + /* + * Variable to save power state + * 1 - TC Cold request cleared. + * 0 - TC Cold request sent. + */ + Name (STAT, 0x1) - Method (_OFF, 0) - { - \_SB.PCI0.TCOF() - STAT = 0 + Method (_STA, 0) + { + Return (STAT) + } + + Method (_ON, 0) + { + \_SB.PCI0.TCON() + STAT = 1 + } + + Method (_OFF, 0) + { + \_SB.PCI0.TCOF() + STAT = 0 + } } - } + } /* End: S0IX */ /* * TCSS xHCI device diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index 273a71e..ff0c5a9 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -27,24 +27,48 @@ Method (_S0W, 0x0) { - Return (0x4) + If (S0IX == 1) { + Return (0x04) + } Else { + Return (0x03) + } } +/* + * Get power resources that are dependent on this device for Operating System Power Management + * to put the device in the D0 device state + */ Method (_PR0) { - If (DUID == 0) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + If (S0IX == 1) { + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + If (DUID == 0) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } } } Method (_PR3) { - If (DUID == 0) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + If (S0IX == 1) { + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + If (DUID == 0) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } } } @@ -53,8 +77,8 @@ */ Method (D3CX, 0, Serialized) { - DD3E = 0 /* Disable DMA RTD3 */ - STAT = 0x1 + DD3E = 0x00 /* Disable DMA RTD3 */ + STAT = 0x01 } /* @@ -62,8 +86,8 @@ */ Method (D3CE, 0, Serialized) { - DD3E = 1 /* Enable DMA RTD3 */ - STAT = 0 + DD3E = 0x01 /* Enable DMA RTD3 */ + STAT = 0x00 } /* @@ -71,7 +95,6 @@ * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0. */ Name (SD3C, 0) - Method (_PS0, 0, Serialized) { } diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 7576564..6b26231 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -267,25 +267,45 @@ Method (_S0W, 0x0, NotSerialized) { - Return (0x4) + If (S0IX == 1) { + Return (0x4) + } Else { + Return (0x3) + } } Method (_PR0) { - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) - } + If (S0IX == 1) { + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } + } Else { + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } + } } Method (_PR3) { - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) - } + If (S0IX == 1) { + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } + } Else { + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } + } } /* diff --git a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl index acbeb30..32aa2f2 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl @@ -30,7 +30,11 @@ Method (_S0W, 0x0, NotSerialized) { - Return (0x4) + If (S0IX == 1) { + Return (0x4) + } Else { + Return (0x3) + } } /* @@ -39,14 +43,16 @@ */ Name (SD3C, 0) -Method (_PR0) -{ - Return (Package () { \_SB.PCI0.D3C }) -} +If (S0IX == 1) { + Method (_PR0) + { + Return (Package () { \_SB.PCI0.D3C }) + } -Method (_PR3) -{ - Return (Package () { \_SB.PCI0.D3C }) + Method (_PR3) + { + Return (Package () { \_SB.PCI0.D3C }) + } } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/59024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb1cc3d6a03cb452ff38ae393a993e881d9b5ff4 Gerrit-Change-Number: 59024 Gerrit-PatchSet: 19 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake/apci: Only use SCM for ChromeOS
by Tim Wawrzynczak (Code Review) 15 Nov '21

15 Nov '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58798 ) Change subject: soc/intel/tigerlake/apci: Only use SCM for ChromeOS ...................................................................... soc/intel/tigerlake/apci: Only use SCM for ChromeOS Software Connection Manager doesn't work with Linux 5.13 or later and results in TBT ports timing out. Not advertising this results in Firmware Connection Manager being used and TBT works correctly. Linux patch: https://github.com/torvalds/linux/commit/c6da62a219d028de10f2e22e93a34c7ee2… Tested on: * StarBook Mk V * System76 Oryx Pro 8 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ib947c3c9cd843e54d4664509c15336178c0bc99e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58798 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Tim Crawford <tcrawford(a)system76.com> --- M src/soc/intel/tigerlake/acpi/tcss.asl 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Tim Crawford: Looks good to me, but someone else must approve diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 2a71b31..cdbf0cc 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -154,6 +154,12 @@ CDW1 |= UNRECOGNIZED_REVISION } Return (Arg3) +#if CONFIG(CHROMEOS) + /* + * Software Connection Manager doesn't work with Linux 5.13 or later and + * results in TBT ports timing out. Not advertising this results in + * Firmware Connection Manager being used and TBT works correctly. + */ } ElseIf (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) { /* * Operating System Capabilities for USB4 @@ -185,6 +191,7 @@ INTER_DOMAIN_USB4_INTERNET_PROTOCOL CDW3 = Local0 Return (Arg3) +#endif } Else { CDW1 |= UNRECOGNIZED_UUID Return (Arg3) -- To view, visit https://review.coreboot.org/c/coreboot/+/58798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib947c3c9cd843e54d4664509c15336178c0bc99e Gerrit-Change-Number: 58798 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [WIP] teleplatforms/D4E4S16P8: Configure ast25xx bootstraps
by build bot (Jenkins) (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36607 ) Change subject: [WIP] teleplatforms/D4E4S16P8: Configure ast25xx bootstraps ...................................................................... Patch Set 11: (3 comments) File src/mainboard/teleplatforms/D4E4S16P8/ast25xx.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133202): https://review.coreboot.org/c/coreboot/+/36607/comment/6a0975b2_cfce1f65 PS11, Line 44: printk(BIOS_INFO, "ast25xx: disable protection status: @ 0x%p 0x%08x\n", scu_protection, locks); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133202): https://review.coreboot.org/c/coreboot/+/36607/comment/f33fb772_536744b1 PS11, Line 47: printk(BIOS_INFO, "ast25xx: scu70_hwtrap current bits: @ 0x%p 0x%08x\n", scu_hwtrap, straps); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133202): https://review.coreboot.org/c/coreboot/+/36607/comment/f16acac1_60d0fc23 PS11, Line 76: printk(BIOS_INFO, "ast25xx: p2p_bridge0: 0x%x; p2p_bridge1: 0x%x\n", p2p_bridge0, p2p_bridge1); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/36607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92195969419f9c38845cb67f294fdab33fb481af Gerrit-Change-Number: 36607 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: David Guckian <d.guckian20(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 04:34:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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