coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya/var/redrix: Update dsm parameters for speeker/tweeter
by Wisley Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Wisley Chen. Wisley Chen has uploaded a new patch set (#3) to the change originally created by Chen Wisley. ( https://review.coreboot.org/c/coreboot/+/59241 ) Change subject: mb/google/brya/var/redrix: Update dsm parameters for speeker/tweeter ...................................................................... mb/google/brya/var/redrix: Update dsm parameters for speeker/tweeter For tuning, redrix needs differnet dsm paramters file for L/R speeker/tweeter. BUG=b:204841998 TEST=build Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I6f93603a6809f9a5aea9f2e554935de5d0457286 --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/59241/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f93603a6809f9a5aea9f2e554935de5d0457286 Gerrit-Change-Number: 59241 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/variants/primus: enable ALC5682I-VS
by Malik Hsu (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Zhuohao Lee. Malik Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59173 ) Change subject: mb/google/brya/variants/primus: enable ALC5682I-VS ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59173/comment/0ea38f25_2835d7ca PS10, Line 9: chang > `change` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5906ef9bb88da7fe450a986bf7dd1ee701227f95 Gerrit-Change-Number: 59173 Gerrit-PatchSet: 11 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 01:45:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: enable ALC5682I-VS
by Malik Hsu (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Malik Hsu, Zhuohao Lee. Hello build bot (Jenkins), Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59173 to look at the new patch set (#11). Change subject: mb/google/brya/variants/primus: enable ALC5682I-VS ...................................................................... mb/google/brya/variants/primus: enable ALC5682I-VS In next phase build, the audio codec will change to ALC5682I-VS BUG=b:205883511 TEST=emerge-brya coreboot chromeos-bootimage and check audio function Signed-off-by: Malik_Hsu <malik_hsu(a)wistron.corp-partner.google.com> Change-Id: I5906ef9bb88da7fe450a986bf7dd1ee701227f95 --- M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus/variant.c 2 files changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/59173/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/59173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5906ef9bb88da7fe450a986bf7dd1ee701227f95 Gerrit-Change-Number: 59173 Gerrit-PatchSet: 11 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/redrix: Update dsm parameters for speeker/tweeter
by Wisley Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Chen Wisley. Wisley Chen has uploaded a new patch set (#2) to the change originally created by Chen Wisley. ( https://review.coreboot.org/c/coreboot/+/59241 ) Change subject: mb/google/brya/var/redrix: Update dsm parameters for speeker/tweeter ...................................................................... mb/google/brya/var/redrix: Update dsm parameters for speeker/tweeter For tuning, redrix needs differnet dsm paramters file for L/R speeker/tweeter. BUG=b:204841998 TEST=build Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I6f93603a6809f9a5aea9f2e554935de5d0457286 --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/59241/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f93603a6809f9a5aea9f2e554935de5d0457286 Gerrit-Change-Number: 59241 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util: Add coreboot-configurator
by Sean Rhodes (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Sean Rhodes, Martin Roth, Matt DeVillier, Tim Wawrzynczak. Hello build bot (Jenkins), Martin Roth, Matt DeVillier, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59256 to look at the new patch set (#5). Change subject: util: Add coreboot-configurator ...................................................................... util: Add coreboot-configurator A simple GUI to change settings in coreboot's CBFS, via the nvramtool utility. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I491922bf55ed87c2339897099634a38f8d055876 --- A util/coreboot-configurator/README.md A util/coreboot-configurator/images/StarLabs_Logo.png A util/coreboot-configurator/images/coreboot-configurator.gif A util/coreboot-configurator/meson.build A util/coreboot-configurator/meson_options.txt A util/coreboot-configurator/src/README.md A util/coreboot-configurator/src/application/AboutDialog.cpp A util/coreboot-configurator/src/application/AboutDialog.h A util/coreboot-configurator/src/application/AboutDialog.ui A util/coreboot-configurator/src/application/Configuration.cpp A util/coreboot-configurator/src/application/Configuration.h A util/coreboot-configurator/src/application/MainWindow.cpp A util/coreboot-configurator/src/application/MainWindow.h A util/coreboot-configurator/src/application/MainWindow.ui A util/coreboot-configurator/src/application/NvramToolCli.cpp A util/coreboot-configurator/src/application/NvramToolCli.h A util/coreboot-configurator/src/application/ToggleSwitch.cpp A util/coreboot-configurator/src/application/ToggleSwitch.h A util/coreboot-configurator/src/application/Util.h A util/coreboot-configurator/src/application/lang.qrc A util/coreboot-configurator/src/application/main.cpp A util/coreboot-configurator/src/application/meson.build A util/coreboot-configurator/src/application/qrc/categories.yaml A util/coreboot-configurator/src/application/qrc/starlabs-logo.png A util/coreboot-configurator/src/application/qrc/toggle-off.svg A util/coreboot-configurator/src/application/qrc/toggle-on.svg A util/coreboot-configurator/src/application/resources.qrc A util/coreboot-configurator/src/meson.build A util/coreboot-configurator/src/resources/coreboot-configurator.desktop A util/coreboot-configurator/src/resources/coreboot_configurator.svg A util/coreboot-configurator/src/resources/meson.build A util/coreboot-configurator/src/resources/org.coreboot.nvramtool.policy A util/coreboot-configurator/src/resources/org.coreboot.reboot.policy 33 files changed, 2,269 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/59256/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I491922bf55ed87c2339897099634a38f8d055876 Gerrit-Change-Number: 59256 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/../thermal: Refactor PCH Thermal Configuration common API
by Subrata Banik (Code Review) 14 Nov '21

14 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59209 to look at the new patch set (#6). Change subject: soc/intel/../thermal: Refactor PCH Thermal Configuration common API ...................................................................... soc/intel/../thermal: Refactor PCH Thermal Configuration common API Thermal configuration has evolved over PCH generations where latest PCH has provided an option to allow thermal configuration using PMC PWRMBASE registers. This patch adds an option for impacted SoC to select the Kconfig for allowing thermal configuration using PMC PCH MMIO space. BUG=b:193774296 TEST=Able to build and boot hatch and adlrvp platform. Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/thermal.h M src/soc/intel/common/block/thermal/Kconfig M src/soc/intel/common/block/thermal/thermal.c 3 files changed, 107 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59209/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/../thermal: Refactor PCH Thermal Configuration common API
by Subrata Banik (Code Review) 14 Nov '21

14 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59209 to look at the new patch set (#5). Change subject: soc/intel/../thermal: Refactor PCH Thermal Configuration common API ...................................................................... soc/intel/../thermal: Refactor PCH Thermal Configuration common API Thermal configuration has evolved over PCH generations where latest PCH has provided an option to allow thermal configuration using PMC PWRMBASE registers. This patch adds an option for impacted SoC to select the Kconfig for allowing thermal configuration using PMC PCH MMIO space. BUG=b:193774296 TEST=Able to build and boot hatch and adlrvp platform. Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/thermal.h M src/soc/intel/common/block/thermal/Kconfig M src/soc/intel/common/block/thermal/thermal.c 3 files changed, 108 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59209/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/inteltool/gpio.c: Correct register name
by Angel Pons (Code Review) 14 Nov '21

14 Nov '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59289 ) Change subject: util/inteltool/gpio.c: Correct register name ...................................................................... util/inteltool/gpio.c: Correct register name The ICH10 and 6-series PCH datasheets indicate that the name of this register is `GP_LVL3`, not `GPIO_LVL3`. Correct the name. Change-Id: I44cc41843c9f7cd0796bd198fb89447d787f155a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/inteltool/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/59289/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 5808204..30b80d8 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -173,7 +173,7 @@ { 0x3C, 4, "RESERVED" }, { 0x40, 4, "GPIO_USE_SEL3" }, { 0x44, 4, "GP_IO_SEL3" }, - { 0x48, 4, "GPIO_LVL3" }, + { 0x48, 4, "GP_LVL3" }, { 0x4c, 4, "RESERVED" }, { 0x50, 4, "RESERVED" }, { 0x54, 4, "RESERVED" }, @@ -227,7 +227,7 @@ { 0x3c, 4, "RESERVED" }, { 0x40, 4, "GPIO_USE_SEL3" }, { 0x44, 4, "GP_IO_SEL3" }, - { 0x48, 4, "GPIO_LVL3" }, + { 0x48, 4, "GP_LVL3" }, { 0x4c, 4, "RESERVED" }, { 0x50, 4, "RESERVED" }, { 0x54, 4, "RESERVED" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/59289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44cc41843c9f7cd0796bd198fb89447d787f155a Gerrit-Change-Number: 59289 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/vell: Generate LP5 RAM ID
by Kevin Chiu (Code Review) 14 Nov '21

14 Nov '21

Attention is currently required from: Kevin Chiu. Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59288 to review the following change. Change subject: mb/google/brya/var/vell: Generate LP5 RAM ID ...................................................................... mb/google/brya/var/vell: Generate LP5 RAM ID Add the support LP5 RAM parts for vell: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) BUG=b:204284866 TEST=emerge-brya coreboot Change-Id: I49745948ebdb25fd98e285defd75714f80271968 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/brya/variants/vell/memory/Makefile.inc M src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt 3 files changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/59288/1 diff --git a/src/mainboard/google/brya/variants/vell/memory/Makefile.inc b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc index 6751a42..8288400 100644 --- a/src/mainboard/google/brya/variants/vell/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc @@ -1,5 +1,8 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/vell/memory src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B diff --git a/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt index fa24790..5160972 100644 --- a/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt @@ -1 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/src/part_id_gen/part_id_gen ADL lp5 src/mainboard/google/brya/variants/vell/memory src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt + DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) +MT62F1G32D4DR-031 WT:B 1 (0001) diff --git a/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt index 9621137..3baf5d4 100644 --- a/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt @@ -9,3 +9,5 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +MT62F512M32D2DR-031 WT:B +MT62F1G32D4DR-031 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/59288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49745948ebdb25fd98e285defd75714f80271968 Gerrit-Change-Number: 59288 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: Add ICH10D PCI ID
by Angel Pons (Code Review) 14 Nov '21

14 Nov '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59287 ) Change subject: util/inteltool: Add ICH10D PCI ID ...................................................................... util/inteltool: Add ICH10D PCI ID Add the PCI device ID for the ICH10D southbridge. While we're at it, also fix up whitespace in inteltool.h of an adjacent definition. Change-Id: I98d88a9ce27d3ddaafd7123ee51b2111a8bef019 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/inteltool/gpio.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/powermgt.c M util/inteltool/rootcmplx.c M util/inteltool/spi.c 6 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/59287/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 53164e1c..5808204 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -943,6 +943,7 @@ defaults_size = ARRAY_SIZE(pp_pch_mobile_defaults); break; case PCI_DEVICE_ID_INTEL_ICH10: + case PCI_DEVICE_ID_INTEL_ICH10D: case PCI_DEVICE_ID_INTEL_ICH10DO: case PCI_DEVICE_ID_INTEL_ICH10R: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 0a8431a..14f6851 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -149,6 +149,7 @@ /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10D, "ICH10D" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10DO, "ICH10DO" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 40b739f..97091c5 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -76,7 +76,8 @@ #define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917 #define PCI_DEVICE_ID_INTEL_ICH10DO 0x3a14 #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 -#define PCI_DEVICE_ID_INTEL_ICH10 0x3a18 +#define PCI_DEVICE_ID_INTEL_ICH10 0x3a18 +#define PCI_DEVICE_ID_INTEL_ICH10D 0x3a1a #define PCI_DEVICE_ID_INTEL_3400_DESKTOP 0x3b00 #define PCI_DEVICE_ID_INTEL_3400_MOBILE 0x3b01 #define PCI_DEVICE_ID_INTEL_P55 0x3b02 diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index f4ebc5a..9e98809 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -780,6 +780,7 @@ pm_registers_size = ARRAY_SIZE(lynxpoint_lp_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH10: + case PCI_DEVICE_ID_INTEL_ICH10D: case PCI_DEVICE_ID_INTEL_ICH10DO: case PCI_DEVICE_ID_INTEL_ICH10R: pmbase = pci_read_word(sb, 0x40) & 0xff80; diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index da9144a..bdafa1e 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -29,6 +29,7 @@ case PCI_DEVICE_ID_INTEL_ICH9M: case PCI_DEVICE_ID_INTEL_ICH9ME: case PCI_DEVICE_ID_INTEL_ICH10: + case PCI_DEVICE_ID_INTEL_ICH10D: case PCI_DEVICE_ID_INTEL_ICH10DO: case PCI_DEVICE_ID_INTEL_ICH10R: case PCI_DEVICE_ID_INTEL_NM10: diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index ad16cb8..1bb5ba2 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -107,6 +107,7 @@ case PCI_DEVICE_ID_INTEL_ICH9M: case PCI_DEVICE_ID_INTEL_ICH9ME: case PCI_DEVICE_ID_INTEL_ICH10: + case PCI_DEVICE_ID_INTEL_ICH10D: case PCI_DEVICE_ID_INTEL_ICH10DO: case PCI_DEVICE_ID_INTEL_ICH10R: case PCI_DEVICE_ID_INTEL_NM10: @@ -259,6 +260,7 @@ case PCI_DEVICE_ID_INTEL_ICH9M: case PCI_DEVICE_ID_INTEL_ICH9ME: case PCI_DEVICE_ID_INTEL_ICH10: + case PCI_DEVICE_ID_INTEL_ICH10D: case PCI_DEVICE_ID_INTEL_ICH10DO: case PCI_DEVICE_ID_INTEL_ICH10R: case PCI_DEVICE_ID_INTEL_NM10: -- To view, visit https://review.coreboot.org/c/coreboot/+/59287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98d88a9ce27d3ddaafd7123ee51b2111a8bef019 Gerrit-Change-Number: 59287 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021