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Change subject: src/mainboard/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8 folder.
......................................................................
Patch Set 17:
(6 comments)
File src/mainboard/teleplatforms/D4E4S16P8/Kconfig:
https://review.coreboot.org/c/coreboot/+/57194/comment/d1cf6131_866f596f
PS17, Line 14: ##
I'll adjust the licenses to one-liners.
https://review.coreboot.org/c/coreboot/+/57194/comment/16c138f7_1e508e96
PS17, Line 42: config ENABLE_FSP_MEMORY_DOWN
Board has DIMM slots, I'll separate this feature as debugging aid, and it's unlikely to be merged.
File src/mainboard/teleplatforms/D4E4S16P8/boardid.c:
https://review.coreboot.org/c/coreboot/+/57194/comment/58493fa2_e7088248
PS17, Line 6: uint8_t board_id(void)
No real board_id(), I will remove.
IMO this would mostly have use if your board had some GPIOs to read PCB revision and firmware would have to that into account somehow. Otherwise, a different board would be typically described as a variant and Kconfig choice.
File src/mainboard/teleplatforms/D4E4S16P8/emmc.h:
https://review.coreboot.org/c/coreboot/+/57194/comment/fa1b28b5_c4f1c978
PS17, Line 11: BL_EMMC_INFORMATION D4E4S16P8_emmc_config[] = {
eMMC is not routed and 0:1c.0 should not be enabled, I'll remove this file
File src/mainboard/teleplatforms/D4E4S16P8/romstage.c:
https://review.coreboot.org/c/coreboot/+/57194/comment/48ed71f4_c92e7aa9
PS17, Line 102: if (!CONFIG(ENABLE_FSP_MEMORY_DOWN))
You would never set this for a board with DIMM slots, except for occasional debug use if reading SPD over SMBus failed. I will separate the spd/ directory and have it available for you, but not likely to be merged.
File src/mainboard/teleplatforms/D4E4S16P8/smbus.c:
https://review.coreboot.org/c/coreboot/+/57194/comment/8cea34c2_fe277647
PS17, Line 81: .device = 0x19df, /* Denverton SMBus0 "Legacy" device id */
This file is not specific to your board, I'll remove it here. We should have a working copy under soc/intel somewhere so the feature this implements can still work if you need it.
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Hello build bot (Jenkins), Дмитрий Понаморев, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36607
to look at the new patch set (#9).
Change subject: [WIP] teleplatforms/D4E4S16P8: Configure ast25xx bootstraps
......................................................................
[WIP] teleplatforms/D4E4S16P8: Configure ast25xx bootstraps
Configure graphics PCI device as VGA using software bootstrap
bits.
TBD: Can we delay this to be done as a common PCI driver.
TBD: Add Kconfig guard.
Change-Id: I92195969419f9c38845cb67f294fdab33fb481af
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/teleplatforms/D4E4S16P8/Makefile.inc
A src/mainboard/teleplatforms/D4E4S16P8/ast25xx.c
M src/soc/intel/denverton_ns/chip.c
M src/soc/intel/denverton_ns/include/soc/ramstage.h
4 files changed, 207 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/36607/9
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59096 )
Change subject: util/lint: Fix linters to work with coreboot-configurator
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59096/comment/94cb2411_73e70b0e
PS5, Line 7: Exclude coreboot-configurator directory from checkpatch
> Maybe "Fix linters to work with coreboot-configurator" since there are 2 linter changes now. […]
Done
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Hello build bot (Jenkins), Martin Roth, Patrick Georgi,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: util/lint: Fix linters to work with coreboot-configurator
......................................................................
util/lint: Fix linters to work with coreboot-configurator
* Exclude .gif files from newline checking
* Exclude coreboot-configurator from checkpatch checking
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I1b07b7b05340409e5c1695cc7bbdea68f8190097
---
M util/lint/lint-007-checkpatch
M util/lint/lint-extended-015-final-newlines
2 files changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/59096/6
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Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58798 )
Change subject: soc/intel/tigerlake/apci: Only use SCM for ChromeOS
......................................................................
Patch Set 13: Code-Review+1
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Change subject: Add ENV_STAGE_SUPPORTS_SMP to clean up spinlock stubs
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59094/comment/4abaa496_a7d92389
PS2, Line 14: IMO commit a98d302fe9 x86/smp/spinlock: Disable thread coop when taking spinlock
: is wrong and should be reverted too.
> Honestly, thinking about this more... […]
Done
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