coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: Kconfig: Show console DEBUG_FUNC if OVERRIDE_LOGLEVEL is set
by Paul Fagerburg (Code Review) 13 Nov '21

13 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59196 ) Change subject: Kconfig: Show console DEBUG_FUNC if OVERRIDE_LOGLEVEL is set ...................................................................... Kconfig: Show console DEBUG_FUNC if OVERRIDE_LOGLEVEL is set Show the DEBUG_FUNC option if COSOLE_OVERRIDE_LOGLEVEL is set, or it will never be available for some mainboards. This was missed in commit cf3dcd6d2975673622c3272e0d7f3e421051fe74 Change-Id: Id2ef287fb39989007f28fc6475209eda0a63c792 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59196 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> --- M src/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jonathan Zhang: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index e1d0c00..44e84bf 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1179,7 +1179,7 @@ endif config DEBUG_FUNC - bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 + bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL default n help This option enables additional function entry and exit debug messages -- To view, visit https://review.coreboot.org/c/coreboot/+/59196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2ef287fb39989007f28fc6475209eda0a63c792 Gerrit-Change-Number: 59196 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/psp_verstage: Reboot on verstage_soc_early_init fail
by Paul Fagerburg (Code Review) 13 Nov '21

13 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59017 ) Change subject: soc/amd/psp_verstage: Reboot on verstage_soc_early_init fail ...................................................................... soc/amd/psp_verstage: Reboot on verstage_soc_early_init fail Calling reboot_into_recovery with NULL context fails. Initializing ctx early also fails because the cmos is not ready until after verstage_soc_early_init. So just reboot and hope for the best. BUG=None TEST=Boot guybrush, suspend/resume guybrush BRANCH=None Change-Id: I7267a14ab048781b8998d3a6f4220de10e7df250 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59017 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c 2 files changed, 9 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Kangheui Won: Looks good to me, approved diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index 7687ac6..f5890d4 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -35,6 +35,7 @@ #define POSTCODE_FMAP_REGION_MISSING 0xC8 #define POSTCODE_AMD_FW_MISSING 0xC9 #define POSTCODE_CMOS_RECOVERY 0xCA +#define POSTCODE_EARLY_INIT_ERROR 0xCB #define POSTCODE_UNMAP_SPI_ROM 0xF0 #define POSTCODE_UNMAP_FCH_DEVICES 0xF1 diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 9f27159..3bfa3e9 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -224,8 +224,14 @@ svc_write_postcode(POSTCODE_EARLY_INIT); retval = verstage_soc_early_init(); if (retval) { - svc_debug_print("verstage_soc_early_init failed\n"); - reboot_into_recovery(NULL, retval); + /* + * If verstage_soc_early_init fails, cmos is probably not + * accessible, so rebooting into recovery is not an option. + * Just reboot and hope for the best. + */ + svc_write_postcode(POSTCODE_EARLY_INIT_ERROR); + svc_debug_print("verstage_soc_early_init failed! -- rebooting\n"); + vboot_reboot(); } svc_debug_print("calling verstage_mainboard_early_init\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/59017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7267a14ab048781b8998d3a6f4220de10e7df250 Gerrit-Change-Number: 59017 Gerrit-PatchSet: 5 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting"
by Paul Fagerburg (Code Review) 13 Nov '21

13 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59149 ) Change subject: Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting" ...................................................................... Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting" This reverts commit ba6fdc892d62741e456ac5628fcd6f869c4cb9af. Reason for revert: Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1), GPP_R6 ~ GPP_R7 should be NF3 for dmic. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I460fd99b4ad4b9c470f692032ff7ea2b51cad388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59149 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/brask/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index ba4bbf8..ffdc285 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -318,9 +318,9 @@ /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* R6 : I2S2_TXD ==> DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* R7 : I2S2_RXD ==> DMIC_DATA1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* S0 : SNDW0_CLK ==> NC */ PAD_NC(GPP_S0, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/59149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I460fd99b4ad4b9c470f692032ff7ea2b51cad388 Gerrit-Change-Number: 59149 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/xeon_sp: Fix size_t type mismatch in print statement
by Paul Fagerburg (Code Review) 13 Nov '21

13 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59054 ) Change subject: soc/intel/xeon_sp: Fix size_t type mismatch in print statement ...................................................................... soc/intel/xeon_sp: Fix size_t type mismatch in print statement The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC romstage/soc/intel/xeon_sp/memmap.o src/soc/intel/xeon_sp/memmap.c: In function 'fill_postcar_frame': src/soc/intel/xeon_sp/memmap.c:39:62: error: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 39 | printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%lx\n", cbmem_base, cbmem_size); | ~~^ ~~~~~~~~~~ | | | | long unsigned int size_t {aka unsigned int} | %x As `cbmem_size` is of type `size_t` use the appropriate length modifier `z`. Change-Id: I1ca77de1ce33ce1e97d7c8895c6e75424f0769f5 Found-by: gcc (Debian 11.2.0-10) 11.2.0 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59054 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Lance Zhao --- M src/soc/intel/xeon_sp/memmap.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Lance Zhao: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index 0af0ad2..b640c2d 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -36,7 +36,7 @@ /* Try account for the CBMEM region currently used and for future use */ cbmem_get_region((void **)&cbmem_base, &cbmem_size); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%lx\n", cbmem_base, cbmem_size); + printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%zx\n", cbmem_base, cbmem_size); /* Assume 4MiB will be enough for future cbmem objects (FSP-S, ramstage, ...) */ cbmem_base -= 4 * MiB; cbmem_base = ALIGN_DOWN(cbmem_base, 4 * MiB); 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ca77de1ce33ce1e97d7c8895c6e75424f0769f5 Gerrit-Change-Number: 59054 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
by Tim Wawrzynczak (Code Review) 13 Nov '21

13 Nov '21

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Paul Menzel, Nick Vaccaro, Julius Werner, Andrey Petrov, Patrick Rudolph, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58253 ) Change subject: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Gerrit-Change-Number: 58253 Gerrit-PatchSet: 9 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 12 Nov 2021 23:50:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake/apci: Only use SCM for ChromeOS
by Tim Wawrzynczak (Code Review) 13 Nov '21

13 Nov '21

Attention is currently required from: Tim Crawford, Sean Rhodes, Jeremy Soller, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58798 ) Change subject: soc/intel/tigerlake/apci: Only use SCM for ChromeOS ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib947c3c9cd843e54d4664509c15336178c0bc99e Gerrit-Change-Number: 58798 Gerrit-PatchSet: 13 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 12 Nov 2021 23:50:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add config option for S3 ACPI
by Tim Wawrzynczak (Code Review) 13 Nov '21

13 Nov '21

Attention is currently required from: Tim Crawford, Sean Rhodes, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59024 ) Change subject: soc/intel/tigerlake: Add config option for S3 ACPI ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb1cc3d6a03cb452ff38ae393a993e881d9b5ff4 Gerrit-Change-Number: 59024 Gerrit-PatchSet: 18 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 12 Nov 2021 23:49:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/mipi_camera: Add support for _DSC field
by Tim Wawrzynczak (Code Review) 13 Nov '21

13 Nov '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Paul Menzel, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58767 ) Change subject: driver/intel/mipi_camera: Add support for _DSC field ...................................................................... Patch Set 10: Code-Review+1 (1 comment) Patchset: PS10: Looks OK to me, the default value is 0 which represents D0 which is what we want for default behavior. -- To view, visit https://review.coreboot.org/c/coreboot/+/58767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b Gerrit-Change-Number: 58767 Gerrit-PatchSet: 10 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 12 Nov 2021 23:48:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEV...
by Tim Wawrzynczak (Code Review) 13 Nov '21

13 Nov '21

Attention is currently required from: Varshit B Pandya, Chen Wisley. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59260 ) Change subject: mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEVICE_SLEEP_D3_COLD ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/redrix/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59260/comment/aee1d9e5_5ee04d0e PS2, Line 346: ACPI_DEVICE_SLEEP_D3_COLD Maybe I'm confused, should the NVM also have the _DSC set to D3cold? this one you want to actually put into D0 to probe? -- To view, visit https://review.coreboot.org/c/coreboot/+/59260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88ea1b87698c63e1bd69367ee857fba3f25c84ea Gerrit-Change-Number: 59260 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 23:41:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/herobrine: Use same I2C/SPI configs for piglin and hoglin
by Douglas Anderson (Code Review) 13 Nov '21

13 Nov '21

Attention is currently required from: Shelley Chen, mturney mturney, Ravi Kumar Bokka, Sudheer Amrabadi. Douglas Anderson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59273 ) Change subject: mb/google/herobrine: Use same I2C/SPI configs for piglin and hoglin ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/herobrine/mainboard.c: https://review.coreboot.org/c/coreboot/+/59273/comment/dcd095c0_a4a3fa03 PS1, Line 56: GSI Ugh. Why would they use GSI for I2C here. I don't think it buys anything... I guess a conversation for another day. -- To view, visit https://review.coreboot.org/c/coreboot/+/59273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14497a205262ac1081c24631e4fd8d39bb804fce Gerrit-Change-Number: 59273 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Fri, 12 Nov 2021 23:37:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021