coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/brya/var/felwinter: Remove USB2 port 0
by EricR Lai (Code Review) 13 Nov '21

13 Nov '21

Attention is currently required from: Nick Vaccaro. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59236 ) Change subject: mb/google/brya/var/felwinter: Remove USB2 port 0 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59236/comment/96d99f01_78269c8a PS1, Line 9: shcematics > `as per schematics` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45d467a80c23d82dc33dcbed176430a758eea403 Gerrit-Change-Number: 59236 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Sat, 13 Nov 2021 03:10:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Remove USB2 port 0
by EricR Lai (Code Review) 13 Nov '21

13 Nov '21

Attention is currently required from: Nick Vaccaro, EricR Lai. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59236 to look at the new patch set (#2). Change subject: mb/google/brya/var/felwinter: Remove USB2 port 0 ...................................................................... mb/google/brya/var/felwinter: Remove USB2 port 0 USB2 port 0 is empty as per schematics. BUG=b:206047996 TEST=USB2 port 0 is disabled. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I45d467a80c23d82dc33dcbed176430a758eea403 --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/59236/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45d467a80c23d82dc33dcbed176430a758eea403 Gerrit-Change-Number: 59236 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/felwinter: Disable PCIE port 6
by EricR Lai (Code Review) 13 Nov '21

13 Nov '21

Attention is currently required from: Nick Vaccaro. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59243 ) Change subject: mb/google/brya/var/felwinter: Disable PCIE port 6 ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59243/comment/4f3fd068_674a1086 PS1, Line 9: as shcematics. > `as per schematics` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30fa897c9310c44545e3df670895639a5144e1de Gerrit-Change-Number: 59243 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Sat, 13 Nov 2021 03:09:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Disable PCIE port 6
by EricR Lai (Code Review) 13 Nov '21

13 Nov '21

Attention is currently required from: Nick Vaccaro. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59243 to look at the new patch set (#3). Change subject: mb/google/brya/var/felwinter: Disable PCIE port 6 ...................................................................... mb/google/brya/var/felwinter: Disable PCIE port 6 PCIE port 6 is empty as per schematics. BUG=b:206047996 TEST=PCIE port 6 is disabled. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I30fa897c9310c44545e3df670895639a5144e1de --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/59243/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30fa897c9310c44545e3df670895639a5144e1de Gerrit-Change-Number: 59243 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/felwinter: Disable PCIE port 6
by EricR Lai (Code Review) 13 Nov '21

13 Nov '21

Attention is currently required from: Nick Vaccaro, EricR Lai. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59243 to look at the new patch set (#2). Change subject: mb/google/brya/var/felwinter: Disable PCIE port 6 ...................................................................... mb/google/brya/var/felwinter: Disable PCIE port 6 PCIE port 6 is empty as pre schematics. BUG=b:206047996 TEST=PCIE port 6 is disabled. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I30fa897c9310c44545e3df670895639a5144e1de --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/59243/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30fa897c9310c44545e3df670895639a5144e1de Gerrit-Change-Number: 59243 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Enable early EC sync
by Boris Mittelberg (Code Review) 13 Nov '21

13 Nov '21

Boris Mittelberg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59274 ) Change subject: mb/google/brya: Enable early EC sync ...................................................................... mb/google/brya: Enable early EC sync Enable VBOOT_EARLY_EC_SYNC in corebot BUG=b:201356952 BRANCH=None TEST=Tested on Brya id 2 Signed-off-by: Boris Mittelberg <bmbm(a)google.com> Change-Id: I6e480d64a5d90d5bb9cf59ed60b7b53af9edf46a --- M src/mainboard/google/brya/Kconfig 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/59274/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 850a78c..d818baa 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -57,7 +57,6 @@ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE - select VBOOT_LID_SWITCH config CHROMEOS_WIFI_SAR bool "Enable SAR options for Chrome OS build" @@ -115,6 +114,10 @@ default "felwinter" if BOARD_GOOGLE_FELWINTER default "anahera" if BOARD_GOOGLE_ANAHERA +config VBOOT + select VBOOT_EARLY_EC_SYNC + select VBOOT_LID_SWITCH + config DIMM_SPD_SIZE default 512 -- To view, visit https://review.coreboot.org/c/coreboot/+/59274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e480d64a5d90d5bb9cf59ed60b7b53af9edf46a Gerrit-Change-Number: 59274 Gerrit-PatchSet: 1 Gerrit-Owner: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/common: Update CPPCv3 Nominal Frequency entry
by Michael Niewöhner (Code Review) 13 Nov '21

13 Nov '21

Attention is currently required from: Tim Wawrzynczak, Sugnan Prabhu S, Ravindra, Sridhar Siricilla, Patrick Rudolph, Ravindra N. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57783 ) Change subject: cpu/intel/common: Update CPPCv3 Nominal Frequency entry ...................................................................... Patch Set 7: (1 comment) File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/57783/comment/b9e03d01_d8032456 PS7, Line 136: CPPC_DWORD(0); > @Tim/Michael, […] Uhm, tbh that sounds wrong... but let's see when you pushed it :-) -- To view, visit https://review.coreboot.org/c/coreboot/+/57783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If39e5e4ac77a71b143cdb5f043fb398abb398ee3 Gerrit-Change-Number: 57783 Gerrit-PatchSet: 7 Gerrit-Owner: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Sat, 13 Nov 2021 01:00:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add variant_espi_gpio_table
by Paul Fagerburg (Code Review) 13 Nov '21

13 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59082 ) Change subject: mb/google/guybrush: Add variant_espi_gpio_table ...................................................................... mb/google/guybrush: Add variant_espi_gpio_table Add separate gpio table for early eSPI bus init. Remove espi GPIO from early_gpio_table. This allows for initializing eSPI separately from other GPIOs. Simplify verstage_mainboard_early_init. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59082 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/google/guybrush/bootblock.c M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/guybrush/verstage.c M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c 6 files changed, 64 insertions(+), 42 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index bffcb0c..1154444 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -31,8 +31,8 @@ void bootblock_mainboard_early_init(void) { uint32_t dword; - size_t base_num_gpios, override_num_gpios; - const struct soc_amd_gpio *base_gpios, *override_gpios; + size_t num_gpios, override_num_gpios; + const struct soc_amd_gpio *gpios, *override_gpios; /* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped on Picasso and older compared to Renoir/Cezanne and newer */ @@ -50,11 +50,12 @@ if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) return; - base_gpios = variant_early_gpio_table(&base_num_gpios); - override_gpios = variant_early_override_gpio_table(&override_num_gpios); + gpios = variant_espi_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); - gpio_configure_pads_with_override(base_gpios, base_num_gpios, - override_gpios, override_num_gpios); + gpios = variant_early_gpio_table(&num_gpios); + override_gpios = variant_early_override_gpio_table(&override_num_gpios); + gpio_configure_pads_with_override(gpios, num_gpios, override_gpios, override_num_gpios); /* Set a timer to make sure there's enough delay for * the Fibocom 350 PCIe init diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index fb01789..6b8c2b7 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -206,10 +206,23 @@ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), /* I2C3_SDA */ PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* ESPI_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* GSC_SOC_INT_L */ PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + +/* Enable UART 0 */ + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + +/* Support EC trusted */ + /* SD_EX_PRSNT_L(Guybrush BoardID 1 only) / EC_IN_RW_OD */ + PAD_GPI(GPIO_91, PULL_NONE), +}; + +static const struct soc_amd_gpio espi_gpio_table[] = { + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* ESPI_SOC_CLK */ PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), /* ESPI1_DATA0 */ @@ -222,16 +235,6 @@ PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), /* ESPI_ALERT_L */ PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), - -/* Enable UART 0 */ - /* UART0_RXD */ - PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), - /* UART0_TXD */ - PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), - -/* Support EC trusted */ - /* SD_EX_PRSNT_L(Guybrush BoardID 1 only) / EC_IN_RW_OD */ - PAD_GPI(GPIO_91, PULL_NONE), }; /* Power-on timing requirements: @@ -344,3 +347,9 @@ *size = ARRAY_SIZE(sleep_gpio_table); return sleep_gpio_table; } + +const __weak struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + return espi_gpio_table; +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 955d170..0dc6c7b 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -40,6 +40,9 @@ /* This function provides GPIO settings before entering sleep. */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size); +/* This function provides GPIO settings for eSPI bus. */ +const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); + bool variant_has_pcie_wwan(void); void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors); diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c index e6434df..17481d2 100644 --- a/src/mainboard/google/guybrush/verstage.c +++ b/src/mainboard/google/guybrush/verstage.c @@ -4,41 +4,45 @@ #include <amdblocks/gpio.h> #include <arch/io.h> #include <baseboard/variants.h> +#include <psp_verstage.h> #include <security/vboot/vboot_common.h> #include <soc/southbridge.h> -static void setup_gpio(void) +void verstage_mainboard_early_init(void) { const struct soc_amd_gpio *gpios, *override_gpios; size_t num_gpios, override_num_gpios; - if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { - gpios = variant_early_gpio_table(&num_gpios); - override_gpios = variant_early_override_gpio_table(&override_num_gpios); + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; - gpio_configure_pads_with_override(gpios, num_gpios, - override_gpios, override_num_gpios); - } + gpios = variant_early_gpio_table(&num_gpios); + override_gpios = variant_early_override_gpio_table(&override_num_gpios); + gpio_configure_pads_with_override(gpios, num_gpios, override_gpios, override_num_gpios); } -void verstage_mainboard_early_init(void) +void verstage_mainboard_espi_init(void) { - setup_gpio(); + const struct soc_amd_gpio *gpios; + size_t num_gpios; + uint32_t dword; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + gpios = variant_espi_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); /* - * TODO : Make common function in cezanne code and just call it - * when PCI access is fixed in the PSP (b/186602472). - * For now the PSP doesn't configure LPC so it should be fine. - */ - if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { - uint32_t dword; - printk(BIOS_DEBUG, "Verstage configure eSPI\n"); - dword = pm_io_read32(PM_SPI_PAD_PU_PD); - dword |= PM_ESPI_CS_USE_DATA2; - pm_io_write32(PM_SPI_PAD_PU_PD, dword); + * TODO : Make common function in cezanne code and just call it + * when PCI access is fixed in the PSP (b/186602472). + * For now the PSP doesn't configure LPC so it should be fine. + */ + dword = pm_io_read32(PM_SPI_PAD_PU_PD); + dword |= PM_ESPI_CS_USE_DATA2; + pm_io_write32(PM_SPI_PAD_PU_PD, dword); - dword = pm_io_read32(PM_ACPI_CONF); - dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; - pm_io_write32(PM_ACPI_CONF, dword); - } + dword = pm_io_read32(PM_ACPI_CONF); + dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; + pm_io_write32(PM_ACPI_CONF, dword); } diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index f5890d4..976bc69 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -48,6 +48,7 @@ void test_svc_calls(void); uint32_t unmap_fch_devices(void); uint32_t verstage_soc_early_init(void); +void verstage_mainboard_espi_init(void); void verstage_soc_init(void); uintptr_t *map_spi_rom(void); diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 3bfa3e9..f3b4256 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -24,6 +24,7 @@ extern char _bss_start, _bss_end; void __weak verstage_mainboard_early_init(void) {} +void __weak verstage_mainboard_espi_init(void) {} void __weak verstage_mainboard_init(void) {} uint32_t __weak get_max_workbuf_size(uint32_t *size) { @@ -233,8 +234,11 @@ svc_debug_print("verstage_soc_early_init failed! -- rebooting\n"); vboot_reboot(); } - svc_debug_print("calling verstage_mainboard_early_init\n"); + printk(BIOS_DEBUG, "calling verstage_mainboard_espi_init\n"); + verstage_mainboard_espi_init(); + + printk(BIOS_DEBUG, "calling verstage_mainboard_early_init\n"); verstage_mainboard_early_init(); svc_write_postcode(POSTCODE_LATE_INIT); -- To view, visit https://review.coreboot.org/c/coreboot/+/59082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8 Gerrit-Change-Number: 59082 Gerrit-PatchSet: 6 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
by Yu-Ping Wu (Code Review) 13 Nov '21

13 Nov '21

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Paul Menzel, Nick Vaccaro, Julius Werner, Andrey Petrov, Patrick Rudolph, Felix Held. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58253 ) Change subject: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Gerrit-Change-Number: 58253 Gerrit-PatchSet: 9 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 13 Nov 2021 00:41:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMA
by Paul Fagerburg (Code Review) 13 Nov '21

13 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59029 ) Change subject: sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMA ...................................................................... sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMA This change adds about 30 KiB to FSP-M. When not using the SPI DMA controller, this change actually has a ~7 ms boot time penalty. When we use the DMA engine, we end up with about a 5 ms decrease. Once we switch to 100 MHz SPI this will help even more since we have effectively eliminated the decompression time. BUG=b:179699789 TEST=Boot nipperkin to OS and take boot time measurements fspm.bin 0x2efc0 fsp 90953 LZMA (233472 decompressed) fspm.bin 0x2cfc0 fsp 121156 LZ4 (233472 decompressed) - FSP-M / no async - | 508 - finished loading body | 177.019 | 179.384 Δ( 2.36, 0.16%) | ... | 970 - loading FSP-M | 0.346 | 0.346 Δ( 0.00, 0.00%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.009 | 0.01 Δ( 0.00, 0.00%) | | 18 - finished LZ4 decompress (ignore for x86) | 53.916 | 59.475 Δ( 5.56, 0.37%) | - FSP-M / async - | 508 - finished loading body | 177.185 | 179.689 Δ( 2.50, 0.18%) | ... | 970 - loading FSP-M | 0.989 | 0.99 Δ( 0.00, 0.00%) | | 17 - starting LZ4 decompress (ignore for x86) | 9.483 | 12.877 Δ( 3.39, 0.24%) | | 18 - finished LZ4 decompress (ignore for x86) | 10.833 | 0.312 Δ(-10.52, -0.75%) | Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I7d0363d27d98d4ed3afc6f802a13ff7986391921 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59029 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Rob Barnes: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index aaa3811..3fb5085 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -20,7 +20,8 @@ select DRIVERS_USB_ACPI select DRIVERS_I2C_DESIGNWARE select DRIVERS_USB_PCI_XHCI - select FSP_COMPRESS_FSP_M_LZMA + select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING + select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING select FSP_COMPRESS_FSP_S_LZ4 select GENERIC_GPIO_LIB select HAVE_ACPI_TABLES -- To view, visit https://review.coreboot.org/c/coreboot/+/59029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d0363d27d98d4ed3afc6f802a13ff7986391921 Gerrit-Change-Number: 59029 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021