coreboot-gerrit November 2021

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Change in coreboot[master]: [WIP] teleplatforms/D4E4S16P8: Configure ast25xx bootstraps
by Kyösti Mälkki (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Kyösti Mälkki, Patrick Rudolph. Hello build bot (Jenkins), Дмитрий Понаморев, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36607 to look at the new patch set (#11). Change subject: [WIP] teleplatforms/D4E4S16P8: Configure ast25xx bootstraps ...................................................................... [WIP] teleplatforms/D4E4S16P8: Configure ast25xx bootstraps Configure graphics PCI device as VGA using software bootstrap bits. TBD: Can we delay this to be done as a common PCI driver. TBD: Add Kconfig guard. Change-Id: I92195969419f9c38845cb67f294fdab33fb481af Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M 3rdparty/blobs M src/mainboard/teleplatforms/D4E4S16P8/Makefile.inc A src/mainboard/teleplatforms/D4E4S16P8/ast25xx.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/denverton_ns/include/soc/ramstage.h 5 files changed, 208 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/36607/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/36607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92195969419f9c38845cb67f294fdab33fb481af Gerrit-Change-Number: 36607 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: David Guckian <d.guckian20(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8
by Kyösti Mälkki (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Дмитрий Понаморев, Mariusz Szafrański, Paul Menzel, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, King Sumo. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57194 ) Change subject: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8 ...................................................................... Patch Set 18: (5 comments) File configs/config.teleplatforms.D4E4S16P8: PS18: This config will not build until 3rdparty/blobs is merged File src/mainboard/teleplatforms/D4E4S16P8/Kconfig: https://review.coreboot.org/c/coreboot/+/57194/comment/8d71e296_b8ca61b3 PS17, Line 42: config ENABLE_FSP_MEMORY_DOWN > Board has DIMM slots, I'll separate this feature as debugging aid, and it's unlikely to be merged. Done File src/mainboard/teleplatforms/D4E4S16P8/boardid.c: https://review.coreboot.org/c/coreboot/+/57194/comment/b87fd4cd_5e19032f PS17, Line 6: uint8_t board_id(void) > No real board_id(), I will remove. […] Done File src/mainboard/teleplatforms/D4E4S16P8/emmc.h: https://review.coreboot.org/c/coreboot/+/57194/comment/e3d390ea_415f510a PS17, Line 11: BL_EMMC_INFORMATION D4E4S16P8_emmc_config[] = { > eMMC is not routed and 0:1c. […] Done File src/mainboard/teleplatforms/D4E4S16P8/romstage.c: https://review.coreboot.org/c/coreboot/+/57194/comment/ddda7ffe_3100ecdf PS17, Line 102: if (!CONFIG(ENABLE_FSP_MEMORY_DOWN)) > You would never set this for a board with DIMM slots, except for occasional debug use if reading SPD […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Gerrit-Change-Number: 57194 Gerrit-PatchSet: 18 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 04:31:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] teleplatforms/D4E4S16P8: Configure ast25xx bootstraps
by build bot (Jenkins) (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36607 ) Change subject: [WIP] teleplatforms/D4E4S16P8: Configure ast25xx bootstraps ...................................................................... Patch Set 10: (3 comments) File src/mainboard/teleplatforms/D4E4S16P8/ast25xx.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133200): https://review.coreboot.org/c/coreboot/+/36607/comment/9121a3f4_7b9b9c44 PS10, Line 44: printk(BIOS_INFO, "ast25xx: disable protection status: @ 0x%p 0x%08x\n", scu_protection, locks); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133200): https://review.coreboot.org/c/coreboot/+/36607/comment/a7afbe33_51e64903 PS10, Line 47: printk(BIOS_INFO, "ast25xx: scu70_hwtrap current bits: @ 0x%p 0x%08x\n", scu_hwtrap, straps); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133200): https://review.coreboot.org/c/coreboot/+/36607/comment/6ffd0f3d_43733333 PS10, Line 76: printk(BIOS_INFO, "ast25xx: p2p_bridge0: 0x%x; p2p_bridge1: 0x%x\n", p2p_bridge0, p2p_bridge1); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/36607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92195969419f9c38845cb67f294fdab33fb481af Gerrit-Change-Number: 36607 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: David Guckian <d.guckian20(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 04:27:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8
by Kyösti Mälkki (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Дмитрий Понаморев, Mariusz Szafrański, Paul Menzel, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, King Sumo. Kyösti Mälkki has uploaded a new patch set (#18) to the change originally created by Дмитрий Понаморев. ( https://review.coreboot.org/c/coreboot/+/57194 ) Change subject: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8 ...................................................................... mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8 These sources are to compile the coreboot firmware image for the teleplatforms D4E4S16P8 motherboard. The board is based on an Intel Atom C3758 processor. Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Signed-off-by: Dmitry Ponamorev <dponamorev(a)gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- A configs/config.teleplatforms.D4E4S16P8 A src/mainboard/teleplatforms/D4E4S16P8/Kconfig A src/mainboard/teleplatforms/D4E4S16P8/Kconfig.name A src/mainboard/teleplatforms/D4E4S16P8/Makefile.inc A src/mainboard/teleplatforms/D4E4S16P8/acpi/mainboard.asl A src/mainboard/teleplatforms/D4E4S16P8/acpi/mainboard_pci_irqs.asl A src/mainboard/teleplatforms/D4E4S16P8/acpi/platform.asl A src/mainboard/teleplatforms/D4E4S16P8/acpi/thermal.asl A src/mainboard/teleplatforms/D4E4S16P8/acpi_tables.c A src/mainboard/teleplatforms/D4E4S16P8/board_info.txt A src/mainboard/teleplatforms/D4E4S16P8/devicetree.cb A src/mainboard/teleplatforms/D4E4S16P8/dsdt.asl A src/mainboard/teleplatforms/D4E4S16P8/gpio.h A src/mainboard/teleplatforms/D4E4S16P8/hsio.c A src/mainboard/teleplatforms/D4E4S16P8/hsio.h A src/mainboard/teleplatforms/D4E4S16P8/ramstage.c A src/mainboard/teleplatforms/D4E4S16P8/romstage.c A src/mainboard/teleplatforms/D4E4S16P8/smbus.c A src/mainboard/teleplatforms/Kconfig A src/mainboard/teleplatforms/Kconfig.name 20 files changed, 1,889 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/57194/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/57194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Gerrit-Change-Number: 57194 Gerrit-PatchSet: 18 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Move typeC AUX configuration to variant
by EricR Lai (Code Review) 15 Nov '21

15 Nov '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59290 ) Change subject: mb/google/brya: Move typeC AUX configuration to variant ...................................................................... mb/google/brya: Move typeC AUX configuration to variant TypeC AUX configuration is variant specific. So move into variant level. BUG=b:205235144 TEST=No typeC port 0 AUX in felwinter. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I02bfea462cf4c6359fd8d5cca4368786ee03bc8b --- M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/brya0/overridetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/59290/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index c89f24f..2204a71 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/alderlake - register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - # GPE configuration register "pmc_gpe0_dw0" = "GPP_A" register "pmc_gpe0_dw1" = "GPP_E" diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 0052d90..bbba955 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -43,6 +43,8 @@ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. register "ext_fivr_settings" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/59290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02bfea462cf4c6359fd8d5cca4368786ee03bc8b Gerrit-Change-Number: 59290 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/vell: Generate LP5 RAM ID
by Shon Wang (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Tim Wawrzynczak, Kevin Chiu. Shon Wang has uploaded a new patch set (#2) to the change originally created by Kevin Chiu. ( https://review.coreboot.org/c/coreboot/+/59288 ) Change subject: mb/google/brya/var/vell: Generate LP5 RAM ID ...................................................................... mb/google/brya/var/vell: Generate LP5 RAM ID Add the support LP5 RAM parts for vell: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) BUG=b:204284866 TEST=emerge-brya coreboot Change-Id: I49745948ebdb25fd98e285defd75714f80271968 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/brya/variants/vell/memory/Makefile.inc M src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt 3 files changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/59288/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49745948ebdb25fd98e285defd75714f80271968 Gerrit-Change-Number: 59288 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/corsola: Add VMCH and VMC for regulator interface
by Hung-Te Lin (Code Review) 15 Nov '21

15 Nov '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59255 ) Change subject: mb/google/corsola: Add VMCH and VMC for regulator interface ...................................................................... mb/google/corsola: Add VMCH and VMC for regulator interface Add VMCH and VMC for providing power of SDCard. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I50fc87415086eb22ff35d157dba38cfd7594cc40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59255 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/regulator.c M src/soc/mediatek/common/include/soc/regulator.h 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/regulator.c b/src/mainboard/google/corsola/regulator.c index 1ddc52c..b1310af 100644 --- a/src/mainboard/google/corsola/regulator.c +++ b/src/mainboard/google/corsola/regulator.c @@ -16,6 +16,8 @@ [MTK_REGULATOR_VCC] = REGULATOR_NOT_SUPPORT, [MTK_REGULATOR_VCCQ] = REGULATOR_NOT_SUPPORT, [MTK_REGULATOR_VDRAM1] = MT6366_VDRAM1, + [MTK_REGULATOR_VMCH] = MT6366_VMCH, + [MTK_REGULATOR_VMC] = MT6366_VMC, }; _Static_assert(ARRAY_SIZE(regulator_id) == MTK_REGULATOR_NUM, "regulator_id size error"); diff --git a/src/soc/mediatek/common/include/soc/regulator.h b/src/soc/mediatek/common/include/soc/regulator.h index 08ce47f..a53d01c 100644 --- a/src/soc/mediatek/common/include/soc/regulator.h +++ b/src/soc/mediatek/common/include/soc/regulator.h @@ -14,6 +14,8 @@ MTK_REGULATOR_VCC, MTK_REGULATOR_VCCQ, MTK_REGULATOR_VDRAM1, + MTK_REGULATOR_VMCH, + MTK_REGULATOR_VMC, MTK_REGULATOR_NUM, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50fc87415086eb22ff35d157dba38cfd7594cc40 Gerrit-Change-Number: 59255 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8186: Add support for regulator VMCH and VMC
by Hung-Te Lin (Code Review) 15 Nov '21

15 Nov '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59254 ) Change subject: soc/mediatek/mt8186: Add support for regulator VMCH and VMC ...................................................................... soc/mediatek/mt8186: Add support for regulator VMCH and VMC Add support for VMCH and VMC of MT6366. TEST=measure voltage 3.3V for VMCH and VMC BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Id8d98b6d827abd4713ee5c216941a9621422c7eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/59254 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/include/soc/mt6366.h M src/soc/mediatek/mt8186/mt6366.c 2 files changed, 124 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/include/soc/mt6366.h b/src/soc/mediatek/mt8186/include/soc/mt6366.h index fc6e09f..76fcf54 100644 --- a/src/soc/mediatek/mt8186/include/soc/mt6366.h +++ b/src/soc/mediatek/mt8186/include/soc/mt6366.h @@ -37,7 +37,13 @@ PMIC_VDRAM1_VOSEL = 0x1626, PMIC_SMPS_ANA_CON0 = 0x1808, PMIC_VDDQ_OP_EN = 0x1b16, + PMIC_LDO_VMC_CON0 = 0x1cc4, + PMIC_LDO_VMC_OP_EN = 0x1cc6, + PMIC_LDO_VMCH_CON0 = 0x1cd8, + PMIC_LDO_VMCH_OP_EN = 0x1cda, PMIC_VSIM2_ANA_CON0 = 0x1e30, + PMIC_VMCH_ANA_CON0 = 0x1e48, + PMIC_VMC_ANA_CON0 = 0x1e4c, PMIC_VDDQ_ELR_0 = 0x1ec4, }; @@ -45,6 +51,8 @@ MT6366_VCORE = 0, MT6366_VDRAM1, MT6366_VDDQ, + MT6366_VMCH, + MT6366_VMC, MT6366_REGULATOR_NUM, }; diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c index f9488bd..e63a264 100644 --- a/src/soc/mediatek/mt8186/mt6366.c +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -560,6 +560,112 @@ udelay(1); } +static u32 pmic_get_vmch_vol(void) +{ + u32 vol_reg, ret; + + vol_reg = pwrap_read_field(PMIC_VMCH_ANA_CON0, 0x7, 8); + + switch (vol_reg) { + case 2: + ret = 2900000; + break; + case 3: + ret = 3000000; + break; + case 5: + ret = 3300000; + break; + default: + printk(BIOS_ERR, "ERROR[%s] VMCH read fail: %d\n", __func__, vol_reg); + ret = 0; + break; + } + return ret; +} + +static void pmic_set_vmch_vol(u32 vmch_uv) +{ + u32 val = 0; + + switch (vmch_uv) { + case 2900000: + val = 2; + break; + case 3000000: + val = 3; + break; + case 3300000: + val = 5; + break; + default: + die("ERROR[%s]: VMCH voltage %u is not support.\n", __func__, vmch_uv); + return; + } + + pwrap_write_field(PMIC_VMCH_ANA_CON0, val, 0x7, 8); + + /* Force SW to turn on */ + pwrap_write_field(PMIC_LDO_VMCH_OP_EN, 1, 0xFF, 0); + pwrap_write_field(PMIC_LDO_VMCH_CON0, 1, 0xFF, 0); +} + +static u32 pmic_get_vmc_vol(void) +{ + u32 vol_reg, ret; + + vol_reg = pwrap_read_field(PMIC_VMC_ANA_CON0, 0xF, 8); + + switch (vol_reg) { + case 0x4: + ret = 1800000; + break; + case 0xA: + ret = 2900000; + break; + case 0xB: + ret = 3000000; + break; + case 0xD: + ret = 3300000; + break; + default: + printk(BIOS_ERR, "ERROR[%s] VMC read fail: %d\n", __func__, vol_reg); + ret = 0; + break; + } + return ret; +} + +static void pmic_set_vmc_vol(u32 vmc_uv) +{ + u32 val = 0; + + switch (vmc_uv) { + case 1800000: + val = 0x4; + break; + case 2900000: + val = 0xA; + break; + case 3000000: + val = 0xB; + break; + case 3300000: + val = 0xD; + break; + default: + die("ERROR[%s]: VMC voltage %u is not support.\n", __func__, vmc_uv); + return; + } + + pwrap_write_field(PMIC_VMC_ANA_CON0, val, 0xF, 8); + + /* Force SW to turn on */ + pwrap_write_field(PMIC_LDO_VMC_OP_EN, 1, 0xFF, 0); + pwrap_write_field(PMIC_LDO_VMC_CON0, 1, 0xFF, 0); +} + static void pmic_wdt_set(void) { /* [5]=1, RG_WDTRSTB_DEB */ @@ -667,6 +773,12 @@ case MT6366_VDDQ: pmic_set_vddq_vol(voltage_uv); break; + case MT6366_VMCH: + pmic_set_vmch_vol(voltage_uv); + break; + case MT6366_VMC: + pmic_set_vmc_vol(voltage_uv); + break; default: printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id); break; @@ -682,6 +794,10 @@ return pmic_get_vdram1_vol(); case MT6366_VDDQ: return pmic_get_vddq_vol(); + case MT6366_VMCH: + return pmic_get_vmch_vol(); + case MT6366_VMC: + return pmic_get_vmc_vol(); default: printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id); break; 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8d98b6d827abd4713ee5c216941a9621422c7eb Gerrit-Change-Number: 59254 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8186: Add AUXADC driver support
by Hung-Te Lin (Code Review) 15 Nov '21

15 Nov '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59253 ) Change subject: soc/mediatek/mt8186: Add AUXADC driver support ...................................................................... soc/mediatek/mt8186: Add AUXADC driver support Add AUXADC controller driver code. TEST=build pass BUG=b:202871018 Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com> Change-Id: I9fb7fd4903d67a2804c31ff404bc0486983c742f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59253 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/include/soc/auxadc.h A src/soc/mediatek/mt8186/include/soc/efuse.h 3 files changed, 49 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 4c89f3d..7d6d2ff 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8186),y) +bootblock-y += ../common/auxadc.c bootblock-y += bootblock.c bootblock-y += ../common/eint_event.c bootblock-y += ../common/flash_controller.c @@ -12,6 +13,7 @@ bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c wdt.c +verstage-y += ../common/auxadc.c verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -19,6 +21,7 @@ verstage-y += ../common/uart.c verstage-y += ../common/wdt.c wdt.c +romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-y += ../common/flash_controller.c @@ -30,6 +33,7 @@ romstage-y += ../common/wdt.c wdt.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c +ramstage-y += ../common/auxadc.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8186/include/soc/auxadc.h b/src/soc/mediatek/mt8186/include/soc/auxadc.h new file mode 100644 index 0000000..13a52e3 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/auxadc.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.9 + */ + +#ifndef SOC_MEDIATEK_MT8186_AUXADC_H +#define SOC_MEDIATEK_MT8186_AUXADC_H + +#include <soc/auxadc_common.h> +#include <soc/infracfg.h> +#include <stdint.h> + +typedef struct mtk_auxadc_regs { + uint32_t con0; + uint32_t con1; + uint32_t con1_set; + uint32_t con1_clr; + uint32_t con2; + uint32_t data[16]; + uint32_t reserved[16]; + uint32_t misc; +} mtk_auxadc_regs; + +static struct mt8186_infracfg_ao_regs *const mtk_infracfg = mt8186_infracfg_ao; + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/efuse.h b/src/soc/mediatek/mt8186/include/soc/efuse.h new file mode 100644 index 0000000..fe3dfff --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/efuse.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8186_EFUSE_H +#define SOC_MEDIATEK_MT8186_EFUSE_H + +#include <soc/addressmap.h> +#include <types.h> + +struct efuse_regs { + uint32_t reserved[130]; + uint32_t adc_cali_reg; +}; + +check_member(efuse_regs, adc_cali_reg, 0x208); +static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE; + +#endif 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fb7fd4903d67a2804c31ff404bc0486983c742f Gerrit-Change-Number: 59253 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/../thermal: Refactor PCH Thermal Configuration common API
by EricR Lai (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Refactor PCH Thermal Configuration common API ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59209/comment/f6e24a04_ce615ec2 PS6, Line 10: /* Fix compilation issue when SoC doesn't have PCH_DEVFN_THERMAL defined */ Maybe we should add back to old soc? Should not be too many. -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 03:07:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021