coreboot-gerrit November 2021

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Change in coreboot[master]: driver/intel/mipi_camera: Add support for _DSC field
by Subrata Banik (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58767 ) Change subject: driver/intel/mipi_camera: Add support for _DSC field ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: > Looks OK to me, the default value is 0 which represents D0 which is what we want for default behavio […] Yes, default it would be `0` as D0. -- To view, visit https://review.coreboot.org/c/coreboot/+/58767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b Gerrit-Change-Number: 58767 Gerrit-PatchSet: 10 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 05:04:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/mipi_camera: Add support for _DSC field
by Subrata Banik (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Paul Menzel, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58767 ) Change subject: driver/intel/mipi_camera: Add support for _DSC field ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b Gerrit-Change-Number: 58767 Gerrit-PatchSet: 10 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 05:03:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Refactor PCH Thermal Configuration common API
by EricR Lai (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Refactor PCH Thermal Configuration common API ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/include/intelblocks/thermal.h: https://review.coreboot.org/c/coreboot/+/59209/comment/3a970362_be78bee1 PS6, Line 6: #define PMC_PWRM_THERMAL_CTEN 0x150c /* Catastrophic Trip Point Enable */ nits: can we align the comment :p should be easier to read. -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 05:00:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Refactor PCH Thermal Configuration common API
by EricR Lai (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Refactor PCH Thermal Configuration common API ...................................................................... Patch Set 6: Code-Review+1 (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59209/comment/88c09c02_cb6b4bb2 PS6, Line 57: static void thermal_or32(uintptr_t addr, uint32_t ordata) I am surprised coreboot didn't have bit wise operation by default which in EDK we used a lot. @Tim, maybe we can add into https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 04:59:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Configure eMMC and SD Card
by Rex-BC Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59292 ) Change subject: soc/mediatek/mt8186: Configure eMMC and SD Card ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/common/include/soc/msdc.h: https://review.coreboot.org/c/coreboot/+/59292/comment/540bd7d3_cb878c35 PS1, Line 171: #endif /* SOC_MEDIATEK_COMMON_MSDC_H */ > adding a line without newline at end of file Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/59292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293 Gerrit-Change-Number: 59292 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 04:59:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Configure eMMC and SD Card
by Rex-BC Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59292 to look at the new patch set (#2). Change subject: soc/mediatek/mt8186: Configure eMMC and SD Card ...................................................................... soc/mediatek/mt8186: Configure eMMC and SD Card The Corsola reference design has both eMMC and SD Card interfaces so we have to configure both in RAM stage. TEST=build pass BUG=b:202871018 Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293 --- M src/mainboard/google/corsola/Kconfig M src/soc/mediatek/common/include/soc/msdc.h M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/msdc.c 4 files changed, 112 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/59292/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293 Gerrit-Change-Number: 59292 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Configure eMMC and SD Card
by build bot (Jenkins) (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Hung-Te Lin. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59292 ) Change subject: soc/mediatek/mt8186: Configure eMMC and SD Card ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/common/include/soc/msdc.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133204): https://review.coreboot.org/c/coreboot/+/59292/comment/ff630dde_cba8a59e PS1, Line 171: #endif /* SOC_MEDIATEK_COMMON_MSDC_H */ adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/59292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293 Gerrit-Change-Number: 59292 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 04:53:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add I2C driver support
by Rex-BC Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59296 ) Change subject: soc/mediatek/mt8186: Add I2C driver support ...................................................................... soc/mediatek/mt8186: Add I2C driver support Add I2C controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Housong Zhang <housong.zhang(a)mediatek.corp-partner.google.com> Change-Id: Ia3800e3a30b0796a64213d3b1ab688580c6ddbca --- M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/i2c.c A src/soc/mediatek/mt8186/include/soc/i2c.h 3 files changed, 208 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/59296/1 diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index cb472ce..0646f6c 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -6,6 +6,7 @@ bootblock-y += ../common/flash_controller.c bootblock-y += gic.c bootblock-y += ../common/gpio.c gpio.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -16,6 +17,7 @@ verstage-y += ../common/auxadc.c verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c +verstage-y += ../common/i2c.c i2c.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c timer.c verstage-y += ../common/uart.c @@ -26,6 +28,7 @@ romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c @@ -37,6 +40,7 @@ ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8186/i2c.c b/src/soc/mediatek/mt8186/i2c.c new file mode 100644 index 0000000..a73f110 --- /dev/null +++ b/src/soc/mediatek/mt8186/i2c.c @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.10 + */ + +#include <assert.h> +#include <console/console.h> +#include <device/mmio.h> +#include <device/i2c_simple.h> +#include <soc/i2c.h> +#include <soc/gpio.h> +#include <timer.h> + +struct mtk_i2c mtk_i2c_bus_controller[] = { + [0] = { + .i2c_regs = (void *)(I2C0_BASE), + .i2c_dma_regs = (void *)(I2C0_DMA_BASE), + }, + [1] = { + .i2c_regs = (void *)(I2C1_BASE), + .i2c_dma_regs = (void *)(I2C1_DMA_BASE), + }, + [2] = { + .i2c_regs = (void *)(I2C2_BASE), + .i2c_dma_regs = (void *)(I2C2_DMA_BASE), + }, + [3] = { + .i2c_regs = (void *)(I2C3_BASE), + .i2c_dma_regs = (void *)(I2C3_DMA_BASE), + }, + [4] = { + .i2c_regs = (void *)(I2C4_BASE), + .i2c_dma_regs = (void *)(I2C4_DMA_BASE), + }, + [5] = { + .i2c_regs = (void *)(I2C5_BASE), + .i2c_dma_regs = (void *)(I2C5_DMA_BASE), + }, + [6] = { + .i2c_regs = (void *)(I2C6_BASE), + .i2c_dma_regs = (void *)(I2C6_DMA_BASE), + }, + [7] = { + .i2c_regs = (void *)(I2C7_BASE), + .i2c_dma_regs = (void *)(I2C7_DMA_BASE), + }, + [8] = { + .i2c_regs = (void *)(I2C8_BASE), + .i2c_dma_regs = (void *)(I2C8_DMA_BASE), + }, + [9] = { + .i2c_regs = (void *)(I2C9_BASE), + .i2c_dma_regs = (void *)(I2C9_DMA_BASE), + }, +}; + +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); + +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { + [0] = { + PAD_FUNC(SDA0, SDA0), + PAD_FUNC(SCL0, SCL0), + }, + [1] = { + PAD_FUNC(SDA1, SDA1), + PAD_FUNC(SCL1, SCL1), + }, + [2] = { + PAD_FUNC(SDA2, SDA2), + PAD_FUNC(SCL2, SCL2), + }, + [3] = { + PAD_FUNC(SDA3, SDA3), + PAD_FUNC(SCL3, SCL3), + }, + [4] = { + PAD_FUNC(SDA4, SDA4), + PAD_FUNC(SCL4, SCL4), + }, + [5] = { + PAD_FUNC(SDA5, SDA5), + PAD_FUNC(SCL5, SCL5), + }, + [6] = { + PAD_FUNC(SDA6, SDA6), + PAD_FUNC(SCL6, SCL6), + }, + [7] = { + PAD_FUNC(SDA7, SDA7), + PAD_FUNC(SCL7, SCL7), + }, + [8] = { + PAD_FUNC(SDA8, SDA8), + PAD_FUNC(SCL8, SCL8), + }, + [9] = { + PAD_FUNC(SDA9, SDA9), + PAD_FUNC(SCL9, SCL9), + }, +}; + +static void mtk_i2c_set_gpio_pinmux(uint8_t bus) +{ + assert(bus < I2C_BUS_NUMBER); + + const struct pad_func *ptr = i2c_funcs[bus]; + for (size_t i = 0; i < 2; i++) { + gpio_set_mode(ptr[i].gpio, ptr[i].func); + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + } +} + +void mtk_i2c_bus_init(uint8_t bus, uint32_t speed) +{ + mtk_i2c_speed_init(bus, speed); + mtk_i2c_set_gpio_pinmux(bus); +} + +void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs) +{ + printk(BIOS_DEBUG, "LTIMING %x\nCLK_DIV %x\n", + read32(&regs->ltiming), + read32(&regs->clock_div)); +} diff --git a/src/soc/mediatek/mt8186/include/soc/i2c.h b/src/soc/mediatek/mt8186/include/soc/i2c.h new file mode 100644 index 0000000..4024e7d --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/i2c.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.10 + */ + +#ifndef SOC_MEDIATEK_MT8186_I2C_H +#define SOC_MEDIATEK_MT8186_I2C_H + +#include <soc/i2c_common.h> +#include <soc/pll.h> + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved0[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved1[36]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved2[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved3[932]; + uint32_t multi_dma; + uint32_t reserved4[2]; + uint32_t rollback; +}; + +/* I2C ID Number*/ +enum { + I2C0, + I2C1, + I2C2, + I2C3, + I2C4, + I2C5, + I2C6, + I2C7, + I2C8, + I2C9, +}; + +#define I2C_BUS_NUMBER 10 +#define MAX_CLOCK_DIV 32 +#define I2C_CLK_HZ (UNIV2PLL_HZ / 20) + +check_member(mt_i2c_regs, multi_dma, 0xf8c); + +void mtk_i2c_bus_init(uint8_t bus, uint32_t speed); + +#endif /* SOC_MEDIATEK_MT8186_I2C_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3800e3a30b0796a64213d3b1ab688580c6ddbca Gerrit-Change-Number: 59296 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: move i2c function to common folder
by Rex-BC Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Hung-Te Lin, Xi Chen. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59295 ) Change subject: soc/mediatek: move i2c function to common folder ...................................................................... soc/mediatek: move i2c function to common folder Move mtk_i2c_max_step_cnt, mtk_i2c_check_ac_timing, mtk_i2c_speed_init and mtk_i2c_calculate_speed to common folder to share with MT8186. TEST=test on tomato ok TEST=emerge-asurada coreboot BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 --- M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/include/soc/i2c_common.h M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8173/include/soc/i2c.h M src/soc/mediatek/mt8183/i2c.c M src/soc/mediatek/mt8183/include/soc/i2c.h M src/soc/mediatek/mt8192/i2c.c M src/soc/mediatek/mt8192/include/soc/i2c.h M src/soc/mediatek/mt8195/i2c.c M src/soc/mediatek/mt8195/include/soc/i2c.h 10 files changed, 282 insertions(+), 257 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59295/1 diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index 1e713db..d526ad3 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -8,6 +8,7 @@ #include <symbols.h> #include <device/mmio.h> #include <soc/i2c.h> +#include <soc/i2c_common.h> #include <device/i2c_simple.h> const struct i2c_spec_values standard_mode_spec = { @@ -281,6 +282,14 @@ seg[0].slave == seg[1].slave); } +static int mtk_i2c_max_step_cnt(uint32_t target_speed) +{ + if (target_speed > I2C_SPEED_FAST_PLUS) + return MAX_HS_STEP_CNT_DIV; + else + return MAX_STEP_CNT_DIV; +} + int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int seg_count) { @@ -307,3 +316,234 @@ return ret; } + +/* + * Check and calculate i2c ac-timing. + * + * Hardware design: + * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src + * xxx_cnt_div = spec->min_xxx_ns / sample_ns + * + * The calculation of sample_ns is rounded down; + * otherwise xxx_cnt_div would be greater than the smallest spec. + * The sda_timing is chosen as the middle value between + * the largest and smallest. + */ +int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src, + uint32_t check_speed, + uint32_t step_cnt, + uint32_t sample_cnt) +{ + const struct i2c_spec_values *spec; + uint32_t su_sta_cnt, low_cnt, high_cnt, max_step_cnt; + uint32_t sda_max, sda_min, clk_ns, max_sta_cnt = 0x100; + uint32_t sample_ns = ((uint64_t)NSECS_PER_SEC * (sample_cnt + 1)) / clk_src; + struct mtk_i2c_ac_timing *ac_timing; + + spec = mtk_i2c_get_spec(check_speed); + + clk_ns = NSECS_PER_SEC / clk_src; + + su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns); + if (su_sta_cnt > max_sta_cnt) + return -1; + + low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); + max_step_cnt = mtk_i2c_max_step_cnt(check_speed); + if (2 * step_cnt > low_cnt && low_cnt < max_step_cnt) { + if (low_cnt > step_cnt) { + high_cnt = 2 * step_cnt - low_cnt; + } else { + high_cnt = step_cnt; + low_cnt = step_cnt; + } + } else { + return -2; + } + + sda_max = spec->max_hd_dat_ns / sample_ns; + if (sda_max > low_cnt) + sda_max = 0; + + sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); + if (sda_min < low_cnt) + sda_min = 0; + + if (sda_min > sda_max) + return -3; + + ac_timing = &mtk_i2c_bus_controller[bus].ac_timing; + if (check_speed > I2C_SPEED_FAST_PLUS) { + ac_timing->hs = I2C_TIME_DEFAULT_VALUE | (sample_cnt << 12) | (high_cnt << 8); + ac_timing->ltiming &= ~GENMASK(15, 9); + ac_timing->ltiming |= (sample_cnt << 12) | (low_cnt << 9); + ac_timing->ext &= ~GENMASK(7, 1); + ac_timing->ext |= (su_sta_cnt << 1) | (1 << 0); + } else { + ac_timing->htiming = (sample_cnt << 8) | (high_cnt); + ac_timing->ltiming = (sample_cnt << 6) | (low_cnt); + ac_timing->ext = (su_sta_cnt << 8) | (1 << 0); + } + + return 0; +} + +/* + * Calculate i2c port speed. + * + * Hardware design: + * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) + * clock_div: fixed in hardware, but may be various in different SoCs + * + * To calculate sample_cnt and step_cnt, we pick the highest bus frequency + * that is still no larger than i2c->speed_hz. + */ +int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src, + uint32_t target_speed, + uint32_t *timing_step_cnt, + uint32_t *timing_sample_cnt) +{ + uint32_t step_cnt; + uint32_t sample_cnt; + uint32_t max_step_cnt; + uint32_t base_sample_cnt = MAX_SAMPLE_CNT_DIV; + uint32_t base_step_cnt; + uint32_t opt_div; + uint32_t best_mul; + uint32_t cnt_mul; + uint32_t clk_div = mtk_i2c_bus_controller[bus].ac_timing.inter_clk_div; + int32_t clock_div_constraint = 0; + int success = 0; + + if (target_speed > I2C_SPEED_HIGH) + target_speed = I2C_SPEED_HIGH; + + max_step_cnt = mtk_i2c_max_step_cnt(target_speed); + base_step_cnt = max_step_cnt; + + /* Find the best combination */ + opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); + best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; + + /* Search for the best pair (sample_cnt, step_cnt) with + * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV + * 0 < step_cnt < max_step_cnt + * sample_cnt * step_cnt >= opt_div + * optimizing for sample_cnt * step_cnt being minimal + */ + for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { + if (sample_cnt == 1) { + if (clk_div != 0) + clock_div_constraint = 1; + else + clock_div_constraint = 0; + } else { + if (clk_div > 1) + clock_div_constraint = 1; + else if (clk_div == 0) + clock_div_constraint = -1; + else + clock_div_constraint = 0; + } + + step_cnt = DIV_ROUND_UP(opt_div + clock_div_constraint, sample_cnt); + if (step_cnt > max_step_cnt) + continue; + + cnt_mul = step_cnt * sample_cnt; + if (cnt_mul >= best_mul) + continue; + + if (mtk_i2c_check_ac_timing(bus, clk_src, + target_speed, step_cnt - 1, + sample_cnt - 1)) + continue; + + success = 1; + best_mul = cnt_mul; + base_sample_cnt = sample_cnt; + base_step_cnt = step_cnt; + if (best_mul == opt_div + clock_div_constraint) + break; + + } + + if (!success) + return -1; + + sample_cnt = base_sample_cnt; + step_cnt = base_step_cnt; + + if (clk_src / (2 * (sample_cnt * step_cnt - clock_div_constraint)) > + target_speed) + return -1; + + *timing_step_cnt = step_cnt - 1; + *timing_sample_cnt = sample_cnt - 1; + + return 0; +} + +void mtk_i2c_speed_init(uint8_t bus, uint32_t speed) +{ + uint32_t max_clk_div = MAX_CLOCK_DIV; + uint32_t clk_src, clk_div, step_cnt, sample_cnt; + uint32_t l_step_cnt, l_sample_cnt; + uint32_t timing_reg_value, ltiming_reg_value; + struct mtk_i2c *bus_ctrl; + + if (bus >= I2C_BUS_NUMBER) { + printk(BIOS_ERR, "%s, error bus num:%d\n", __func__, bus); + return; + } + + bus_ctrl = &mtk_i2c_bus_controller[bus]; + + for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { + clk_src = I2C_CLK_HZ / clk_div; + bus_ctrl->ac_timing.inter_clk_div = clk_div - 1; + + if (speed > I2C_SPEED_FAST_PLUS) { + /* Set master code speed register */ + if (mtk_i2c_calculate_speed(bus, clk_src, I2C_SPEED_FAST, + &l_step_cnt, &l_sample_cnt)) + continue; + + timing_reg_value = (l_sample_cnt << 8) | l_step_cnt; + + /* Set the high speed mode register */ + if (mtk_i2c_calculate_speed(bus, clk_src, speed, + &step_cnt, &sample_cnt)) + continue; + + ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt | + (sample_cnt << 12) | (step_cnt << 9); + bus_ctrl->ac_timing.inter_clk_div = (clk_div - 1) << 8 | (clk_div - 1); + } else { + if (mtk_i2c_calculate_speed(bus, clk_src, speed, + &l_step_cnt, &l_sample_cnt)) + continue; + + timing_reg_value = (l_sample_cnt << 8) | l_step_cnt; + + /* Disable the high speed transaction */ + bus_ctrl->ac_timing.hs = I2C_TIME_CLR_VALUE; + + ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt; + } + + break; + } + + if (clk_div > max_clk_div) { + printk(BIOS_ERR, "%s, cannot support %d hz on i2c-%d\n", __func__, speed, bus); + return; + } + + /* Init i2c bus timing register */ + write32(&bus_ctrl->i2c_regs->clock_div, bus_ctrl->ac_timing.inter_clk_div); + write32(&bus_ctrl->i2c_regs->timing, bus_ctrl->ac_timing.htiming); + write32(&bus_ctrl->i2c_regs->ltiming, bus_ctrl->ac_timing.ltiming); + write32(&bus_ctrl->i2c_regs->hs, bus_ctrl->ac_timing.hs); + write32(&bus_ctrl->i2c_regs->ext_conf, bus_ctrl->ac_timing.ext); +} diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h index 72ec46a..17f0fa36 100644 --- a/src/soc/mediatek/common/include/soc/i2c_common.h +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -143,4 +143,14 @@ const struct i2c_spec_values *mtk_i2c_get_spec(uint32_t speed); void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs); +int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src, + uint32_t check_speed, + uint32_t step_cnt, + uint32_t sample_cnt); +int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src, + uint32_t target_speed, + uint32_t *timing_step_cnt, + uint32_t *timing_sample_cnt); +void mtk_i2c_speed_init(uint8_t bus, uint32_t speed); + #endif diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index ff803c3..dd4629d 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -6,9 +6,6 @@ #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/i2c.h> -#include <soc/pll.h> - -#define I2C_CLK_HZ (AXI_HZ / 16) struct mtk_i2c mtk_i2c_bus_controller[7] = { /* i2c0 setting */ @@ -52,6 +49,9 @@ } }; +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); + #define I2CTAG "[I2C][PL] " #if CONFIG(DEBUG_I2C) diff --git a/src/soc/mediatek/mt8173/include/soc/i2c.h b/src/soc/mediatek/mt8173/include/soc/i2c.h index e6f0140..02a2181 100644 --- a/src/soc/mediatek/mt8173/include/soc/i2c.h +++ b/src/soc/mediatek/mt8173/include/soc/i2c.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8173_I2C_H #include <soc/i2c_common.h> +#include <soc/pll.h> /* I2C Register */ struct mt_i2c_regs { @@ -35,6 +36,10 @@ uint32_t transfer_aux_len; }; +#define I2C_CLK_HZ (AXI_HZ / 16) +#define I2C_BUS_NUMBER 7 +#define MAX_CLOCK_DIV 32 + check_member(mt_i2c_regs, debug_stat, 0x64); void mtk_i2c_bus_init(uint8_t bus); diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c index 3e53a72..193f4b9 100644 --- a/src/soc/mediatek/mt8183/i2c.c +++ b/src/soc/mediatek/mt8183/i2c.c @@ -2,12 +2,9 @@ #include <assert.h> #include <device/mmio.h> -#include <soc/pll.h> #include <soc/i2c.h> #include <soc/gpio.h> -#define I2C_CLK_HZ (UNIVPLL_HZ / 20) - struct mtk_i2c mtk_i2c_bus_controller[] = { /* i2c0 setting */ { @@ -52,7 +49,8 @@ }, }; -#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); struct pad_func { gpio_t gpio; @@ -103,7 +101,7 @@ } } -static void mtk_i2c_speed_init(uint8_t bus) +static void mtk_i2c_speed_init_soc(uint8_t bus) { uint8_t step_div; const uint8_t clock_div = 5; @@ -132,7 +130,7 @@ void mtk_i2c_bus_init(uint8_t bus) { - mtk_i2c_speed_init(bus); + mtk_i2c_speed_init_soc(bus); mtk_i2c_set_gpio_pinmux(bus); } diff --git a/src/soc/mediatek/mt8183/include/soc/i2c.h b/src/soc/mediatek/mt8183/include/soc/i2c.h index e70cf47..ebe75fa 100644 --- a/src/soc/mediatek/mt8183/include/soc/i2c.h +++ b/src/soc/mediatek/mt8183/include/soc/i2c.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8183_I2C_H #include <soc/i2c_common.h> +#include <soc/pll.h> /* I2C Register */ struct mt_i2c_regs { @@ -39,6 +40,10 @@ uint32_t rollback; }; +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) +#define I2C_BUS_NUMBER 7 +#define MAX_CLOCK_DIV 32 + check_member(mt_i2c_regs, multi_dma, 0xf8c); void mtk_i2c_bus_init(uint8_t bus); diff --git a/src/soc/mediatek/mt8192/i2c.c b/src/soc/mediatek/mt8192/i2c.c index a76b039..5f1e3a0 100644 --- a/src/soc/mediatek/mt8192/i2c.c +++ b/src/soc/mediatek/mt8192/i2c.c @@ -2,11 +2,9 @@ #include <assert.h> #include <device/mmio.h> -#include <soc/pll.h> #include <soc/i2c.h> #include <soc/gpio.h> -#define I2C_CLK_HZ (UNIVPLL_HZ / 20) #define I2C_FULL_DUTY 100 #define I2C_HALF_DUTY 50 #define I2C_ADJUSTED_DUTY 45 @@ -64,7 +62,8 @@ }, }; -#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); struct pad_func { gpio_t gpio; @@ -127,7 +126,7 @@ } } -static void mtk_i2c_speed_init(uint8_t bus) +static void mtk_i2c_speed_init_soc(uint8_t bus) { uint8_t step_div; const uint8_t clock_div = 5; @@ -178,7 +177,7 @@ void mtk_i2c_bus_init(uint8_t bus) { - mtk_i2c_speed_init(bus); + mtk_i2c_speed_init_soc(bus); mtk_i2c_set_gpio_pinmux(bus); } diff --git a/src/soc/mediatek/mt8192/include/soc/i2c.h b/src/soc/mediatek/mt8192/include/soc/i2c.h index 72a9af1..fbf41e6 100644 --- a/src/soc/mediatek/mt8192/include/soc/i2c.h +++ b/src/soc/mediatek/mt8192/include/soc/i2c.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8192_I2C_H #include <soc/i2c_common.h> +#include <soc/pll.h> /* I2C Register */ struct mt_i2c_regs { @@ -39,6 +40,10 @@ uint32_t rollback; }; +#define I2C_BUS_NUMBER 10 +#define MAX_CLOCK_DIV 32 +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) + check_member(mt_i2c_regs, multi_dma, 0xf8c); void mtk_i2c_bus_init(uint8_t bus); diff --git a/src/soc/mediatek/mt8195/i2c.c b/src/soc/mediatek/mt8195/i2c.c index 1a10eef..6a34e0f 100644 --- a/src/soc/mediatek/mt8195/i2c.c +++ b/src/soc/mediatek/mt8195/i2c.c @@ -4,13 +4,10 @@ #include <console/console.h> #include <device/mmio.h> #include <device/i2c_simple.h> -#include <soc/pll.h> #include <soc/i2c.h> #include <soc/gpio.h> #include <timer.h> -#define I2C_CLK_HZ (UNIVPLL_HZ / 20) - struct mtk_i2c mtk_i2c_bus_controller[] = { [0] = { .i2c_regs = (void *)(I2C_BASE), @@ -54,7 +51,8 @@ }, }; -#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); struct pad_func { gpio_t gpio; @@ -111,245 +109,6 @@ } } -static int mtk_i2c_max_step_cnt(uint32_t target_speed) -{ - if (target_speed > I2C_SPEED_FAST_PLUS) - return MAX_HS_STEP_CNT_DIV; - else - return MAX_STEP_CNT_DIV; -} - -/* - * Check and calculate i2c ac-timing. - * - * Hardware design: - * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src - * xxx_cnt_div = spec->min_xxx_ns / sample_ns - * - * The calculation of sample_ns is rounded down; - * otherwise xxx_cnt_div would be greater than the smallest spec. - * The sda_timing is chosen as the middle value between - * the largest and smallest. - */ -static int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src, - uint32_t check_speed, - uint32_t step_cnt, - uint32_t sample_cnt) -{ - const struct i2c_spec_values *spec; - uint32_t su_sta_cnt, low_cnt, high_cnt, max_step_cnt; - uint32_t sda_max, sda_min, clk_ns, max_sta_cnt = 0x100; - uint32_t sample_ns = ((uint64_t)NSECS_PER_SEC * (sample_cnt + 1)) / clk_src; - struct mtk_i2c_ac_timing *ac_timing; - - spec = mtk_i2c_get_spec(check_speed); - - clk_ns = NSECS_PER_SEC / clk_src; - - su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns); - if (su_sta_cnt > max_sta_cnt) - return -1; - - low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); - max_step_cnt = mtk_i2c_max_step_cnt(check_speed); - if (2 * step_cnt > low_cnt && low_cnt < max_step_cnt) { - if (low_cnt > step_cnt) { - high_cnt = 2 * step_cnt - low_cnt; - } else { - high_cnt = step_cnt; - low_cnt = step_cnt; - } - } else { - return -2; - } - - sda_max = spec->max_hd_dat_ns / sample_ns; - if (sda_max > low_cnt) - sda_max = 0; - - sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); - if (sda_min < low_cnt) - sda_min = 0; - - if (sda_min > sda_max) - return -3; - - ac_timing = &mtk_i2c_bus_controller[bus].ac_timing; - if (check_speed > I2C_SPEED_FAST_PLUS) { - ac_timing->hs = I2C_TIME_DEFAULT_VALUE | (sample_cnt << 12) | (high_cnt << 8); - ac_timing->ltiming &= ~GENMASK(15, 9); - ac_timing->ltiming |= (sample_cnt << 12) | (low_cnt << 9); - ac_timing->ext &= ~GENMASK(7, 1); - ac_timing->ext |= (su_sta_cnt << 1) | (1 << 0); - } else { - ac_timing->htiming = (sample_cnt << 8) | (high_cnt); - ac_timing->ltiming = (sample_cnt << 6) | (low_cnt); - ac_timing->ext = (su_sta_cnt << 8) | (1 << 0); - } - - return 0; -} - -/* - * Calculate i2c port speed. - * - * Hardware design: - * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) - * clock_div: fixed in hardware, but may be various in different SoCs - * - * To calculate sample_cnt and step_cnt, we pick the highest bus frequency - * that is still no larger than i2c->speed_hz. - */ -static int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src, - uint32_t target_speed, - uint32_t *timing_step_cnt, - uint32_t *timing_sample_cnt) -{ - uint32_t step_cnt; - uint32_t sample_cnt; - uint32_t max_step_cnt; - uint32_t base_sample_cnt = MAX_SAMPLE_CNT_DIV; - uint32_t base_step_cnt; - uint32_t opt_div; - uint32_t best_mul; - uint32_t cnt_mul; - uint32_t clk_div = mtk_i2c_bus_controller[bus].ac_timing.inter_clk_div; - int32_t clock_div_constraint = 0; - int success = 0; - - if (target_speed > I2C_SPEED_HIGH) - target_speed = I2C_SPEED_HIGH; - - max_step_cnt = mtk_i2c_max_step_cnt(target_speed); - base_step_cnt = max_step_cnt; - - /* Find the best combination */ - opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); - best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; - - /* Search for the best pair (sample_cnt, step_cnt) with - * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV - * 0 < step_cnt < max_step_cnt - * sample_cnt * step_cnt >= opt_div - * optimizing for sample_cnt * step_cnt being minimal - */ - for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { - if (sample_cnt == 1) { - if (clk_div != 0) - clock_div_constraint = 1; - else - clock_div_constraint = 0; - } else { - if (clk_div > 1) - clock_div_constraint = 1; - else if (clk_div == 0) - clock_div_constraint = -1; - else - clock_div_constraint = 0; - } - - step_cnt = DIV_ROUND_UP(opt_div + clock_div_constraint, sample_cnt); - if (step_cnt > max_step_cnt) - continue; - - cnt_mul = step_cnt * sample_cnt; - if (cnt_mul >= best_mul) - continue; - - if (mtk_i2c_check_ac_timing(bus, clk_src, - target_speed, step_cnt - 1, - sample_cnt - 1)) - continue; - - success = 1; - best_mul = cnt_mul; - base_sample_cnt = sample_cnt; - base_step_cnt = step_cnt; - if (best_mul == opt_div + clock_div_constraint) - break; - - } - - if (!success) - return -1; - - sample_cnt = base_sample_cnt; - step_cnt = base_step_cnt; - - if (clk_src / (2 * (sample_cnt * step_cnt - clock_div_constraint)) > - target_speed) - return -1; - - *timing_step_cnt = step_cnt - 1; - *timing_sample_cnt = sample_cnt - 1; - - return 0; -} - -static void mtk_i2c_speed_init(uint8_t bus, uint32_t speed) -{ - uint32_t max_clk_div = MAX_CLOCK_DIV; - uint32_t clk_src, clk_div, step_cnt, sample_cnt; - uint32_t l_step_cnt, l_sample_cnt; - uint32_t timing_reg_value, ltiming_reg_value; - struct mtk_i2c *bus_ctrl; - - if (bus >= I2C_BUS_NUMBER) { - printk(BIOS_ERR, "%s, error bus num:%d\n", __func__, bus); - return; - } - - bus_ctrl = &mtk_i2c_bus_controller[bus]; - - for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { - clk_src = I2C_CLK_HZ / clk_div; - bus_ctrl->ac_timing.inter_clk_div = clk_div - 1; - - if (speed > I2C_SPEED_FAST_PLUS) { - /* Set master code speed register */ - if (mtk_i2c_calculate_speed(bus, clk_src, I2C_SPEED_FAST, - &l_step_cnt, &l_sample_cnt)) - continue; - - timing_reg_value = (l_sample_cnt << 8) | l_step_cnt; - - /* Set the high speed mode register */ - if (mtk_i2c_calculate_speed(bus, clk_src, speed, - &step_cnt, &sample_cnt)) - continue; - - ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt | - (sample_cnt << 12) | (step_cnt << 9); - bus_ctrl->ac_timing.inter_clk_div = (clk_div - 1) << 8 | (clk_div - 1); - } else { - if (mtk_i2c_calculate_speed(bus, clk_src, speed, - &l_step_cnt, &l_sample_cnt)) - continue; - - timing_reg_value = (l_sample_cnt << 8) | l_step_cnt; - - /* Disable the high speed transaction */ - bus_ctrl->ac_timing.hs = I2C_TIME_CLR_VALUE; - - ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt; - } - - break; - } - - if (clk_div > max_clk_div) { - printk(BIOS_ERR, "%s, cannot support %d hz on i2c-%d\n", __func__, speed, bus); - return; - } - - /* Init i2c bus timing register */ - write32(&bus_ctrl->i2c_regs->clock_div, bus_ctrl->ac_timing.inter_clk_div); - write32(&bus_ctrl->i2c_regs->timing, bus_ctrl->ac_timing.htiming); - write32(&bus_ctrl->i2c_regs->ltiming, bus_ctrl->ac_timing.ltiming); - write32(&bus_ctrl->i2c_regs->hs, bus_ctrl->ac_timing.hs); - write32(&bus_ctrl->i2c_regs->ext_conf, bus_ctrl->ac_timing.ext); -} - void mtk_i2c_bus_init(uint8_t bus, uint32_t speed) { mtk_i2c_speed_init(bus, speed); diff --git a/src/soc/mediatek/mt8195/include/soc/i2c.h b/src/soc/mediatek/mt8195/include/soc/i2c.h index 743faa1..bbdc9e8 100644 --- a/src/soc/mediatek/mt8195/include/soc/i2c.h +++ b/src/soc/mediatek/mt8195/include/soc/i2c.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8195_I2C_H #include <soc/i2c_common.h> +#include <soc/pll.h> /* I2C Register */ struct mt_i2c_regs { @@ -52,7 +53,10 @@ I2C7, }; +#define I2C_BUS_NUMBER 8 #define MAX_CLOCK_DIV 32 +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) + check_member(mt_i2c_regs, multi_dma, 0xf8c); void mtk_i2c_bus_init(uint8_t bus, uint32_t speed); -- To view, visit https://review.coreboot.org/c/coreboot/+/59295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 Gerrit-Change-Number: 59295 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: add early initialization for eMMC
by Rex-BC Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59294 ) Change subject: soc/mediatek/mt8186: add early initialization for eMMC ...................................................................... soc/mediatek/mt8186: add early initialization for eMMC Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to access eMMC in the very early stage (for example, depthcharge needs it 20ms after started) so we have to start initialization in coreboot. TEST=boot kernel from eMMC ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I3bc06b1fc506b1d6f54f7f456117d22477a87e29 --- M src/soc/mediatek/mt8186/msdc.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/59294/1 diff --git a/src/soc/mediatek/mt8186/msdc.c b/src/soc/mediatek/mt8186/msdc.c index f1c2004..7e5541a 100644 --- a/src/soc/mediatek/mt8186/msdc.c +++ b/src/soc/mediatek/mt8186/msdc.c @@ -58,6 +58,8 @@ /* set eMMC cmd/dat/clk pins driving to 8mA */ SET32_BITFIELDS(gpio_base, MSDC0_DRV, MSDC0_DRV_VALUE); + + mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE); } void mtk_msdc_configure_sdcard(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/59294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bc06b1fc506b1d6f54f7f456117d22477a87e29 Gerrit-Change-Number: 59294 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021