coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/dell/optiplex_9010/devicetree.cb: Enable missing GPEs
by Patrick Rudolph (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59526 ) Change subject: mb/dell/optiplex_9010/devicetree.cb: Enable missing GPEs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4480921a294f35a0dfe1e5acd90d55f6fb4c85b4 Gerrit-Change-Number: 59526 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 06:37:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT
by Patrick Rudolph (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski, Angel Pons. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59523 ) Change subject: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/northbridge/intel/sandybridge/romstage.c: https://review.coreboot.org/c/coreboot/+/59523/comment/a7166941_450eae11 PS2, Line 78: #if CONFIG(INTEL_TXT) use if(CONFIG(INTEL_TXT)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/59523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b912f121593fa55c11813262f09be1a1055e950 Gerrit-Change-Number: 59523 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 06:36:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed
by Patrick Rudolph (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59521 ) Change subject: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59521/comment/f8fcad53_ad833c4e PS2, Line 10: memory on a TXT enabled platform. Previosuly on Sandybridge raminit the this MSR is actually written in init_dram_ddr3(). Do you need to remove the code in src/northbridge/intel/sandybridge/raminit.c at some point? -- To view, visit https://review.coreboot.org/c/coreboot/+/59521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd29d163a2310f0b574fc72d575f23088ab1d11d Gerrit-Change-Number: 59521 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 06:35:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Pick the config VBOOT_ALWAYS_ENABLE_DISPLAY
by shkim (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: SH Kim. Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59534 to review the following change. Change subject: mb/google/dedede/var/bugzzy: Pick the config VBOOT_ALWAYS_ENABLE_DISPLAY ...................................................................... mb/google/dedede/var/bugzzy: Pick the config VBOOT_ALWAYS_ENABLE_DISPLAY Currently the touch screen doesn't work on normal mode on bugzzy. The panel power is required for the built-in touch screen, but it doesn't come up when probing touch screen device on normal mode since firmware doesn't initiaize graphics because there is no firmware screen display on normal mode. This change picks the config VBOOT_ALWAYS_ENABLE_DISPLAY for buggzy to hold the panel power on early OS phase. It will take additional boot time. BUG=b:205496327 BRANCH=dedede TEST=build firmware and verified touch screen worked. Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Change-Id: I133b91ff24ce665351a25fd9e0f85db998a6dfed --- M src/mainboard/google/dedede/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/59534/1 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 78b9fd5..6ebeda8 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -151,6 +151,7 @@ select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select VBOOT_ALWAYS_ENABLE_DISPLAY config BOARD_GOOGLE_CORORI bool "-> Corori" -- To view, visit https://review.coreboot.org/c/coreboot/+/59534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I133b91ff24ce665351a25fd9e0f85db998a6dfed Gerrit-Change-Number: 59534 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/genesyslogic/gl9750: Add driver for Genesys Logic GL9750
by Ben Chuang (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Tim Wawrzynczak, Paul Menzel. Ben Chuang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59429 ) Change subject: drivers/genesyslogic/gl9750: Add driver for Genesys Logic GL9750 ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59429/comment/2e85bfdb_032f9898 PS1, Line 14: > could you add […] Yes, done. File src/drivers/genesyslogic/gl9750/gl9750.c: https://review.coreboot.org/c/coreboot/+/59429/comment/a667d851_7474964a PS1, Line 7: #include <device/path.h> > unused? Yes, Unused, thank you. The unused variable 'reg' has also been deleted. https://review.coreboot.org/c/coreboot/+/59429/comment/64f28208_b692ccd0 PS1, Line 22: /* Disable ASPM L0s support */ > Please add a comment, why this needs to be disabled. Done File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/59429/comment/aaaba985_794e72df PS1, Line 2069: #define PCI_DEVICE_ID_GLI_9750 0x9750 > Please sort the list. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d60cef41baade7457a159d3ce2f8d2e6b66e71c Gerrit-Change-Number: 59429 Gerrit-PatchSet: 2 Gerrit-Owner: Ben Chuang <benchuanggli(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Greg Tu <greg.tu(a)genesyslogic.com.tw> Gerrit-CC: HsuanYang Chen <ynop77(a)gmail.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 06:23:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Fix GETSEC checks in romstage
by Patrick Rudolph (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59520 ) Change subject: security/intel/txt: Fix GETSEC checks in romstage ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9103041498f557b85019a56e1252090a4fcd0c9 Gerrit-Change-Number: 59520 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 06:21:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt/ramstage.c: Fix HEAP_ACM element size calculation
by Patrick Rudolph (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59519 ) Change subject: security/intel/txt/ramstage.c: Fix HEAP_ACM element size calculation ...................................................................... Patch Set 2: (2 comments) File src/security/intel/txt/ramstage.c: https://review.coreboot.org/c/coreboot/+/59519/comment/e164ddc3_c76da5f2 PS2, Line 271: * FIXME: these calculations handle the lack of SINIT ACM in CBFS. maybe we can use 2 structs, one with NumAcms == 1 and one with NumAcms == 2. I don't think that there are any other cases. https://review.coreboot.org/c/coreboot/+/59519/comment/ff8f3afa_359581f4 PS2, Line 278: size this will fix the HEAP_EXTDATA_TYPE_ACM size for case NumAcms == 1, but it then will not point to HEAP_EXTDATA_TYPE_END. -- To view, visit https://review.coreboot.org/c/coreboot/+/59519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c37a66d96e1ca3fb4d3f665e3ad35c6f1c5c1e Gerrit-Change-Number: 59519 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 06:21:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/genesyslogic/gl9750: Add driver for Genesys Logic GL9750
by Ben Chuang (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Ben Chuang. Hello build bot (Jenkins), Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59429 to look at the new patch set (#2). Change subject: drivers/genesyslogic/gl9750: Add driver for Genesys Logic GL9750 ...................................................................... drivers/genesyslogic/gl9750: Add driver for Genesys Logic GL9750 The device is a PCIe Gen1 to SD 3.0 card reader controller to be used in the Chromebook. The datasheet name is GL9750S and the revision is 01. The patch disables ASPM L0s. BUG=b:206014046 TEST=Verify GL9750 enters L1 by observing CLKREQ# de-asserts. Signed-off-by: Ben Chuang <benchuanggli(a)gmail.com> Change-Id: I6d60cef41baade7457a159d3ce2f8d2e6b66e71c --- A src/drivers/genesyslogic/gl9750/Kconfig A src/drivers/genesyslogic/gl9750/Makefile.inc A src/drivers/genesyslogic/gl9750/gl9750.c A src/drivers/genesyslogic/gl9750/gl9750.h M src/include/device/pci_ids.h 5 files changed, 72 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/59429/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d60cef41baade7457a159d3ce2f8d2e6b66e71c Gerrit-Change-Number: 59429 Gerrit-PatchSet: 2 Gerrit-Owner: Ben Chuang <benchuanggli(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Greg Tu <greg.tu(a)genesyslogic.com.tw> Gerrit-CC: HsuanYang Chen <ynop77(a)gmail.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ben Chuang <benchuanggli(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/intel/txt: Allow platforms without FIT enable Intel TXT
by Patrick Rudolph (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59518 ) Change subject: security/intel/txt: Allow platforms without FIT enable Intel TXT ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2858c8de9396449a0ee30837a98fab05570a6259 Gerrit-Change-Number: 59518 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 06:12:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Use common txt_reset_platform
by Patrick Rudolph (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59517 ) Change subject: security/intel/txt: Use common txt_reset_platform ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I561458044860ee5a26f7d61bcff1c407fa1533f2 Gerrit-Change-Number: 59517 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 06:11:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021