coreboot-gerrit November 2021

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Change in coreboot[master]: security/intel/txt: Remove unused region device
by Patrick Rudolph (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59515 ) Change subject: security/intel/txt: Remove unused region device ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98afba35403d5d2cd9eeb7df6d1ca0171894e9d4 Gerrit-Change-Number: 59515 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 06:11:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Correct reporting of chipset production fuse state
by Patrick Rudolph (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59514 ) Change subject: security/intel/txt: Correct reporting of chipset production fuse state ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/security/intel/txt/common.c: https://review.coreboot.org/c/coreboot/+/59514/comment/770cb5e0_a83bb1e9 PS2, Line 155: reg = read64((void *)TXT_VER_QPIIF); this seems to be 32bit register as well -- To view, visit https://review.coreboot.org/c/coreboot/+/59514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic86c5a9e1d162630a1cf61435d1014edabf104b0 Gerrit-Change-Number: 59514 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 06:10:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Add support for DPR
by Patrick Rudolph (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski, Angel Pons. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59512 ) Change subject: nb/intel/sandybridge: Add support for DPR ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia22e49ba58709acfa0afe0921aa71d83cc06c129 Gerrit-Change-Number: 59512 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 06:08:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/trogdor: change pin define for quackingstick
by Sheng-Liang Pan (Code Review) 21 Nov '21

21 Nov '21

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59533 ) Change subject: mb/google/trogdor: change pin define for quackingstick ...................................................................... mb/google/trogdor: change pin define for quackingstick change TP_EN pin to GPIO_67 for quackingstick BUG=b:206862167 BRANCH=trogdor TEST=make Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I7cc1083111f46cd3489cbbb9e579c34dc972b0b0 --- M src/mainboard/google/trogdor/board.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/59533/1 diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index 534cfe9..7245743 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -23,7 +23,7 @@ #define GPIO_AVDD_LCD_ENABLE GPIO(88) #define GPIO_AVEE_LCD_ENABLE GPIO(21) #define GPIO_VDD_RESET_1V8 GPIO(87) -#define GPIO_TP_EN GPIO(85) +#define GPIO_TP_EN (CONFIG(BOARD_GOOGLE_QUACKINGSTICK) ? GPIO(67) : GPIO(85)) #define GPIO_EDP_BRIDGE_ENABLE dead_code_t(gpio_t) #define GPIO_EN_PP3300_DX_EDP dead_code_t(gpio_t) #define GPIO_PS8640_EDP_BRIDGE_PD_L dead_code_t(gpio_t) -- To view, visit https://review.coreboot.org/c/coreboot/+/59533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cc1083111f46cd3489cbbb9e579c34dc972b0b0 Gerrit-Change-Number: 59533 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEV...
by Varshit B Pandya (Code Review) 21 Nov '21

21 Nov '21

Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59260 ) Change subject: mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEVICE_SLEEP_D3_COLD ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/brya/variants/redrix/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59260/comment/85f7ae0c_2ac7882c PS3, Line 355: GPP_D16 > Not for this change, but we need to improve this driver... […] I am a bit confused, which other place are we exposing D16 to driver ? -- To view, visit https://review.coreboot.org/c/coreboot/+/59260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88ea1b87698c63e1bd69367ee857fba3f25c84ea Gerrit-Change-Number: 59260 Gerrit-PatchSet: 4 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arec <arec.kao(a)intel.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 04:25:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: remove tmp bar assignment for cpu crashlog
by Kane Chen (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Tim Wawrzynczak, Arthur Heymans, Patrick Rudolph. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59355 ) Change subject: soc/intel/alderlake: remove tmp bar assignment for cpu crashlog ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/alderlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/59355/comment/99a27ef6_4f318db6 PS8, Line 213: printk(BIOS_DEBUG, "cpu crashlog bar addr: 0x%X\n", : pci_read_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0)); > No need to read PCI config space then. Use the resources attached to the device. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7e6772be51ec4f26ef31fed6cb2bddef8ffc6be Gerrit-Change-Number: 59355 Gerrit-PatchSet: 9 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 03:51:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: remove tmp bar assignment for cpu crashlog
by Kane Chen (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Francois Toguo Fotso, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59355 to look at the new patch set (#9). Change subject: soc/intel/alderlake: remove tmp bar assignment for cpu crashlog ...................................................................... soc/intel/alderlake: remove tmp bar assignment for cpu crashlog When the cpu_cl_discovery is called, coreboot actually assigns a BAR to cpu crashlog pci device. Hence, we don't need to assign a tmp BAR for cpu crashlog pci device BUG=b:195327879 TEST=Found BERT table is created and the tcss function is ok in depthcharge Change-Id: Ib7e6772be51ec4f26ef31fed6cb2bddef8ffc6be Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> --- M src/soc/intel/alderlake/crashlog.c 1 file changed, 2 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/59355/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/59355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7e6772be51ec4f26ef31fed6cb2bddef8ffc6be Gerrit-Change-Number: 59355 Gerrit-PatchSet: 9 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/net/r8168: Add customized_mleds to support RTL8125
by build bot (Jenkins) (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59531 ) Change subject: drivers/net/r8168: Add customized_mleds to support RTL8125 ...................................................................... Patch Set 1: (1 comment) File src/drivers/net/r8168.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133977): https://review.coreboot.org/c/coreboot/+/59531/comment/979ad33e_04a64d3d PS1, Line 256: printk(BIOS_DEBUG, "r8168: Customized LED 0x%x\n", config->customized_mleds[i]); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/59531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b05a859dc0a0d2b8d6b35d6491fc88f7077cb92 Gerrit-Change-Number: 59531 Gerrit-PatchSet: 1 Gerrit-Owner: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 03:29:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/net/r8168: Add customized_mleds to support RTL8125
by Rory Liu (Code Review) 21 Nov '21

21 Nov '21

Rory Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59531 ) Change subject: drivers/net/r8168: Add customized_mleds to support RTL8125 ...................................................................... drivers/net/r8168: Add customized_mleds to support RTL8125 The Realtek RTL8125 have four registers for each led, therefore add customized[] to support register array. BUG=b:193750191 TEST=emerge-brask coreboot chromeos-bootimage Signed-off-by: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Change-Id: I4b05a859dc0a0d2b8d6b35d6491fc88f7077cb92 --- M src/drivers/net/chip.h M src/drivers/net/r8168.c M src/include/device/pci_ids.h M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brask/overridetree.cb 5 files changed, 38 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/59531/1 diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h index 9b6a4e5..a29def3 100644 --- a/src/drivers/net/chip.h +++ b/src/drivers/net/chip.h @@ -8,6 +8,7 @@ struct drivers_net_config { uint16_t customized_leds; + uint16_t customized_mleds[]; unsigned int wake; /* Wake pin for ACPI _PRW */ /* Does the device have a power resource? */ diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 5606859..7b08c54 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -28,7 +28,8 @@ #define CMD_REG 0x37 #define CMD_REG_RESET 0x10 -#define CMD_LED0_LED1 0x18 +//#define CMD_LED0_LED1 0x18 +#define CMD_LEDSEL[4] {0x18, 0x86, 0x84, 0x96} #define CFG_9346 0x50 #define CFG_9346_LOCK 0x00 @@ -249,8 +250,19 @@ if (!config) return; - /* Read the customized LED setting from devicetree */ - printk(BIOS_DEBUG, "r8168: Customized LED 0x%x\n", config->customized_leds); + if (dev->subsystem_device == PCI_DEVICE_ID_REALTEK_8125) { + for (i = 0; i < 4; i++) { + /* Read the customized LED setting from devicetree */ + printk(BIOS_DEBUG, "r8168: Customized LED 0x%x\n", config->customized_mleds[i]); + + /* Set customized LED registers */ + outw(config->customized_mleds[i], io_base + CMD_LEDSEL[i]); + printk(BIOS_DEBUG, "r8168: read back LED setting as 0x%x\n", + inw(io_base + CMD_LEDSEL[i])); + } + } else if (dev->subsystem_device == PCI_DEVICE_ID_REALTEK_8111) { + /* Read the customized LED setting from devicetree */ + printk(BIOS_DEBUG, "r8168: Customized LED 0x%x\n", config->customized_leds); /* * Refer to RTL8111H datasheet 7.2 Customizable LED Configuration @@ -267,10 +279,11 @@ * FC Bit12 Bit13 Bit14 Bit15 */ - /* Set customized LED registers */ - outw(config->customized_leds, io_base + CMD_LED0_LED1); - printk(BIOS_DEBUG, "r8168: read back LED setting as 0x%x\n", - inw(io_base + CMD_LED0_LED1)); + /* Set customized LED registers */ + outw(config->customized_leds, io_base + CMD_LEDSEL[0]); + printk(BIOS_DEBUG, "r8168: read back LED setting as 0x%x\n", + inw(io_base + CMD_LEDSEL[0])); + } } static void r8168_init(struct device *dev) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e820d5a..424ed32 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -1283,8 +1283,9 @@ #define PCI_DEVICE_ID_REALTEK_8029 0x8029 #define PCI_DEVICE_ID_REALTEK_8129 0x8129 #define PCI_DEVICE_ID_REALTEK_8139 0x8139 -#define PCI_DEVICE_ID_REALTEK_8168 0x8168 -#define PCI_DEVICE_ID_REALTEK_8125 0x8125 +#define PCI_DEVICE_ID_REALTEK_8168 0x8168 +#define PCI_DEVICE_ID_REALTEK_8125 0x8125 +#define PCI_DEVICE_ID_REALTEK_8111 0x8111 #define PCI_VENDOR_ID_TYAN 0x10f1 #define PCI_VENDOR_ID_XILINX 0x10ee diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 70729c9..00d0e79 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -7,6 +7,9 @@ config BOARD_GOOGLE_BASEBOARD_BRASK def_bool n select SPD_CACHE_IN_FMAP + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE + if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index 3805666..3420f58 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -79,6 +79,17 @@ device generic 0 alias dptf_policy on end end end + device ref pcie_rp7 on + chip drivers/net + register "customized_mleds" = "{ + [0] = 0x0e09, ## 05af + [1] = 0x0e12, + [2] = 0x0e24, + [3] = 0x0e3f + }" + device pci 00.0 on end + end + end # RTL8125 Ethernet NIC device ref pcie4_0 on # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/59531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b05a859dc0a0d2b8d6b35d6491fc88f7077cb92 Gerrit-Change-Number: 59531 Gerrit-PatchSet: 1 Gerrit-Owner: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/variants/brask: Set PL and PsysPL
by Hou-hsun Lee (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Nick Vaccaro, Zhuohao Lee, Alan Huang. Hou-hsun Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58241 ) Change subject: mb/google/brya/variants/brask: Set PL and PsysPL ...................................................................... Patch Set 12: (1 comment) File src/mainboard/google/brya/variants/brask/ramstage.c: https://review.coreboot.org/c/coreboot/+/58241/comment/9c30a251_6e4e04e8 PS12, Line 23: { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 135, 135 }, The psys_pmax_power should be same (257W) for all SKUs. But seems the psys_pmax_power was not used in your implementation, is my understanding correct? -- To view, visit https://review.coreboot.org/c/coreboot/+/58241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 Gerrit-Change-Number: 58241 Gerrit-PatchSet: 12 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 03:04:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021