coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/alderlake: Add get powerinfo support
by Sumeet R Pawnikar (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59190 ) Change subject: soc/intel/alderlake: Add get powerinfo support ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: moving this change to specific system/board brya -- To view, visit https://review.coreboot.org/c/coreboot/+/59190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e7ea3b34130abd1bc09e3e90d1666a929c88c5b Gerrit-Change-Number: 59190 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 08:17:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
by Ravindra (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Patrick Rudolph. Ravindra has uploaded a new patch set (#11) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/55364 ) Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init ...................................................................... soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init The patch enables cse_fw_sync() before DRAM initialization. BUG=b:175516533 TEST=Dependency with CSE Litev16.0.15.1545 integration Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 2 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/55364/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/55364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Gerrit-Change-Number: 55364 Gerrit-PatchSet: 11 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: TEST
by Robert Chen (Code Review) 22 Nov '21

22 Nov '21

Robert Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/57202 ) Change subject: TEST ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/57202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7d3572dfdb3158439296f7ede8c04e58bce1e20 Gerrit-Change-Number: 57202 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: TEST3
by Robert Chen (Code Review) 22 Nov '21

22 Nov '21

Robert Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/57827 ) Change subject: TEST3 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/57827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad864acbe9d32fee1faefa6076aeca0ac9ff47cf Gerrit-Change-Number: 57827 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h`
by Subrata Banik (Code Review) 22 Nov '21

22 Nov '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59510 ) Change subject: soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h` ...................................................................... soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h` This patch removes unused header inclusion as <intelblocks/thermal.h> from several SoC finalize.c files. Change-Id: Ic9ac0ffb352686af22cc9d11b61f904238eef278 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59510 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/soc/intel/alderlake/finalize.c M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/jasperlake/finalize.c M src/soc/intel/tigerlake/finalize.c 4 files changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index aa136d4..589ea59 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -19,7 +19,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> -#include <intelblocks/thermal.h> #include <intelpch/lockdown.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index d415a1d..ba1b2c4 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -11,7 +11,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> -#include <intelblocks/thermal.h> #include <intelpch/lockdown.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 40b5294..a3d4328 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -11,7 +11,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> -#include <intelblocks/thermal.h> #include <intelpch/lockdown.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 3bbd002..b50529b 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -17,7 +17,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> -#include <intelblocks/thermal.h> #include <intelpch/lockdown.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/59510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9ac0ffb352686af22cc9d11b61f904238eef278 Gerrit-Change-Number: 59510 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add the CnviDdrRfim configuration
by Ronak Kanabar (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar, Subrata Banik, Sridhar Siricilla, Srinidhi N Kaushik, Patrick Rudolph. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58132 ) Change subject: soc/intel/alderlake: Add the CnviDdrRfim configuration ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/58132/comment/00323845_1e7c5e00 PS6, Line 532: /* CNVi DDR RFIM Enable/Disable : * Default 0. Setting this to 1 disables CNVi DDR RFIM. : */ : bool CnviDdrRfimDisable; > Sorry if I'm not clear, in the devicetree, fields that are not explicitly set, will default to 0. […] Done File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/58132/comment/d5316d26_7b61b5a2 PS6, Line 211: (config->CnviDdrRfimDisable) > Ack Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518 Gerrit-Change-Number: 58132 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 07:56:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add the CnviDdrRfim configuration
by Ronak Kanabar (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Sumeet R Pawnikar, Subrata Banik, Sridhar Siricilla, Ronak Kanabar, Srinidhi N Kaushik, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar, Subrata Banik, Sridhar Siricilla, Srinidhi N Kaushik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58132 to look at the new patch set (#7). Change subject: soc/intel/alderlake: Add the CnviDdrRfim configuration ...................................................................... soc/intel/alderlake: Add the CnviDdrRfim configuration FSP v2374_01 introduced new FSPM UPD CnviDdrRfim. Add CnviDdrRfim config to control the CnviDdrRfim UPD from devicetree. Setting CnviDdrRfim to 1 enable CNVi DDR RFIM BUG=b:201724512 BRANCH=None TEST=Build and boot brya with debug FSP and verify CnviDdrRfim UPD value. Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/58132/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/58132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518 Gerrit-Change-Number: 58132 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add ADLP 4+4+2 power configurations
by Curtis Chen (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Curtis Chen, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59483 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Add ADLP 4+4+2 power configurations ...................................................................... soc/intel/alderlake: Add ADLP 4+4+2 power configurations Map exist PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 4+4+2 45W SKU power related settings. BUG=b:193864533 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/vr_config.c 4 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/59483/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731 Gerrit-Change-Number: 59483 Gerrit-PatchSet: 4 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/gimble: Configure Acoustic noise mitigation
by Mark Hsieh (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59535 ) Change subject: mb/google/brya/var/gimble: Configure Acoustic noise mitigation ...................................................................... Patch Set 1: Code-Review+1 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/59535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2be3d30403284b98276c837adefd91aa62c971e4 Gerrit-Change-Number: 59535 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 22 Nov 2021 07:31:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/dell/optiplex_9010/Kconfig: Select Super I/O UART availability
by Patrick Rudolph (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59522 ) Change subject: mb/dell/optiplex_9010/Kconfig: Select Super I/O UART availability ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1b270d49660fd60b6a91194167467c4453e1b6b Gerrit-Change-Number: 59522 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 06:37:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021