coreboot-gerrit November 2021

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Change in coreboot[master]: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads
by Alexander Couzens (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Evgeny Zinoviev, Patrick Rudolph. Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59527 ) Change subject: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: It only happened on suspend-resume. AFAIR it was quite easy to reproduce if you do a couple suspend-resumes you should find it. I guessed the coreboot resume path was too fast for the me with a recent archlinux/linux kernel (from the commit time). -- To view, visit https://review.coreboot.org/c/coreboot/+/59527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a Gerrit-Change-Number: 59527 Gerrit-PatchSet: 2 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 01:46:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads
by Alexander Couzens (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Evgeny Zinoviev, Patrick Rudolph. Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59527 ) Change subject: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a Gerrit-Change-Number: 59527 Gerrit-PatchSet: 2 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 01:45:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/mb/brya: Enable crashlog on brya
by Kane Chen (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Gaggery Tsai, Francois Toguo Fotso, Tim Wawrzynczak. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59486 ) Change subject: src/mb/brya: Enable crashlog on brya ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59486/comment/f52f17e2_9eb82d43 PS4, Line 9: helpis > helps? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4bbe5d7cece0c6c5fc170460d55ac820054abb9 Gerrit-Change-Number: 59486 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 01:36:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mb/brya: Enable crashlog on brya
by Kane Chen (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Gaggery Tsai, Francois Toguo Fotso, Kane Chen, Tim Wawrzynczak. Hello Gaggery Tsai, build bot (Jenkins), Francois Toguo Fotso, Tim Wawrzynczak, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59486 to look at the new patch set (#5). Change subject: src/mb/brya: Enable crashlog on brya ...................................................................... src/mb/brya: Enable crashlog on brya Enabling crashlog helps partners to debug hang issues efficiently. BUG=b:195327879 TEST=Found BERT table is created and the tcss function is ok in depthcharge. Warm/cold/suspend_stress test pass 50 cycles on gimble Change-Id: Ib4bbe5d7cece0c6c5fc170460d55ac820054abb9 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/59486/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4bbe5d7cece0c6c5fc170460d55ac820054abb9 Gerrit-Change-Number: 59486 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Revert "mb/google/brya/anahera: Disable autonomous GPIO power managem...
by Wisley Chen (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Chen Wisley. Wisley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58810 ) Change subject: Revert "mb/google/brya/anahera: Disable autonomous GPIO power management" ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > The CL fixing S0ix has landed, do you still want this one? If the fix already landed, I can abandon this one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24aa5578aed35319b3613595433329e6aed31fe1 Gerrit-Change-Number: 58810 Gerrit-PatchSet: 2 Gerrit-Owner: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 01:32:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads
by Evgeny Zinoviev (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Alexander Couzens, Patrick Rudolph. Hello Alexander Couzens, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59527 to look at the new patch set (#2). Change subject: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads ...................................................................... mb/lenovo: Enable MEI on Sandy Bridge ThinkPads It was already enabled on T520 and L520, but disabled on X220, T420 and T420s. On X220, it was disabled by 0793afe9. I can't reproduce those issues today. Also: - it breaks the me_disable feature, - we already have a Kconfig option to hide MEI in case of errors, - it will be hidden on disabled, recovery, firmware update paths anyway. Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/59527/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a Gerrit-Change-Number: 59527 Gerrit-PatchSet: 2 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads
by Evgeny Zinoviev (Code Review) 21 Nov '21

21 Nov '21

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59527 ) Change subject: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads ...................................................................... mb/lenovo: Enable MEI on Sandy Bridge ThinkPads It was already enabled on T520 and L520, but disabled on X220, T420 and T420s. On X220, it was disabled by 0793afe9. I can't reproduce those issues today. Also: - it breaks the me_disable feature, - we already have a Kconfig option to hide MEI in case of errors, - it will be hidden on disabled, recovery, firmware update paths anyway. Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb A src/southbridge/intel/bd82x6x/me_reset.c 4 files changed, 31 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/59527/1 diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index e42e519..457ccbe 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -61,7 +61,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index ab98ca0..32736a8 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -63,7 +63,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 53eb23a..b239d64 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -60,7 +60,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/southbridge/intel/bd82x6x/me_reset.c b/src/southbridge/intel/bd82x6x/me_reset.c new file mode 100644 index 0000000..4b9fef7 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/me_reset.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +void set_global_reset(bool enable) +{ +#ifdef __SIMPLE_DEVICE__ + u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); +#else + struct device *lpc = pcidev_on_root(0x1f, 0); + u32 etr3 = pci_read_config32(lpc, ETR3); +#endif + + /* Clear CF9 Without Resume Well Reset Enable */ + etr3 &= ~ETR3_CWORWRE; + + /* CF9GR indicates a Global Reset */ + if (enable) + etr3 |= ETR3_CF9GR; + else + etr3 &= ~ETR3_CF9GR; + +#ifdef __SIMPLE_DEVICE__ + pci_write_config32(PCH_LPC_DEV, ETR3, etr3); +#else + pci_write_config32(lpc, ETR3, etr3); +#endif +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a Gerrit-Change-Number: 59527 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/txt: Implement GETSEC PARAMETER dumping
by build bot (Jenkins) (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59516 ) Change subject: security/intel/txt: Implement GETSEC PARAMETER dumping ...................................................................... Patch Set 2: (2 comments) File src/security/intel/txt/logging.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133967): https://review.coreboot.org/c/coreboot/+/59516/comment/274810a9_fa066313 PS2, Line 253: if (txt_feature_flags & GETSEC_PARAMS_TXT_EXT_CRTM_SUPPORT) { braces {} are not necessary for any arm of this statement Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133967): https://review.coreboot.org/c/coreboot/+/59516/comment/eabdf1b3_fad93a63 PS2, Line 259: if (txt_feature_flags & GETSEC_PARAMS_TXT_EXT_MACHINE_CHECK) { braces {} are not necessary for any arm of this statement -- To view, visit https://review.coreboot.org/c/coreboot/+/59516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b2c8337a8d86000a5b43788840d15146b662598 Gerrit-Change-Number: 59516 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 21 Nov 2021 22:06:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/dell/optiplex_9010/romstage.c: Add interrupt routing map
by Michał Żygowski (Code Review) 21 Nov '21

21 Nov '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59525 to look at the new patch set (#3). Change subject: mb/dell/optiplex_9010/romstage.c: Add interrupt routing map ...................................................................... mb/dell/optiplex_9010/romstage.c: Add interrupt routing map Dumped from the Dell BIOS version A30. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ifdc41a1e6627b68813fb264aed7e30df58fc6d54 --- M src/mainboard/dell/optiplex_9010/romstage.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/59525/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdc41a1e6627b68813fb264aed7e30df58fc6d54 Gerrit-Change-Number: 59525 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/intel/txt: Allow platforms without FIT enable Intel TXT
by Michał Żygowski (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59518 ) Change subject: security/intel/txt: Allow platforms without FIT enable Intel TXT ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > I don't see the need for this. […] True. Removed CPU_INTEL_FIRMWARE_INTERFACE_TABLE dependency -- To view, visit https://review.coreboot.org/c/coreboot/+/59518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2858c8de9396449a0ee30837a98fab05570a6259 Gerrit-Change-Number: 59518 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 21 Nov 2021 22:01:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2021