coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: security/intel/txt: Implement GETSEC PARAMETER dumping
by Michał Żygowski (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59516 ) Change subject: security/intel/txt: Implement GETSEC PARAMETER dumping ...................................................................... Patch Set 2: (1 comment) File src/security/intel/txt/common.c: https://review.coreboot.org/c/coreboot/+/59516/comment/72f62bb5_e67cf971 PS1, Line 445: printk(BIOS_DEBUG, " SMCTRL available: "); > keep using above coding style Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b2c8337a8d86000a5b43788840d15146b662598 Gerrit-Change-Number: 59516 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 21 Nov 2021 22:00:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Correct reporting of chipset production fuse state
by Michał Żygowski (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59514 ) Change subject: security/intel/txt: Correct reporting of chipset production fuse state ...................................................................... Patch Set 2: (1 comment) File src/security/intel/txt/common.c: https://review.coreboot.org/c/coreboot/+/59514/comment/f102cdca_0942c71d PS1, Line 152: read64 > the spec says you should do a 4byte read. also reg is only 4 bytes. You are right. I missed it. Fixed -- To view, visit https://review.coreboot.org/c/coreboot/+/59514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic86c5a9e1d162630a1cf61435d1014edabf104b0 Gerrit-Change-Number: 59514 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 21 Nov 2021 21:59:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Add support for DPR
by Michał Żygowski (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59512 ) Change subject: nb/intel/sandybridge: Add support for DPR ...................................................................... Patch Set 2: (1 comment) File src/northbridge/intel/sandybridge/northbridge.c: https://review.coreboot.org/c/coreboot/+/59512/comment/6e44f2df_f1da8e06 PS1, Line 196: struct resource *resource = new_resource(dev, index++); > use reserved_ram_resource() Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia22e49ba58709acfa0afe0921aa71d83cc06c129 Gerrit-Change-Number: 59512 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 21 Nov 2021 21:58:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Fix GETSEC checks in romstage
by Michał Żygowski (Code Review) 21 Nov '21

21 Nov '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59520 to look at the new patch set (#2). Change subject: security/intel/txt: Fix GETSEC checks in romstage ...................................................................... security/intel/txt: Fix GETSEC checks in romstage IA32_FEATURE_CONTROL does not need to be checked by BIOS, in fact these bits are needed only by SENTER and SINIT ACM. ACM ENTERACCS does not check these bits according to Intel SDM. Also noticed that the lock bit of IA32_FEATURE_CONTROL cannot be cleared by issuing neither global reset nor full reset on Sandybridge/Ivybridge platforms which results in a reset loop. However, check the IA32_FEATURE_CONTROL SENTER bits in ramstage where the register is properly set on all cores already. TEST=Run ACM SCLEAN on Dell OptiPlex 9010 with i7-3770/Q77 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie9103041498f557b85019a56e1252090a4fcd0c9 --- M src/security/intel/txt/getsec.c M src/security/intel/txt/romstage.c 2 files changed, 31 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/59520/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9103041498f557b85019a56e1252090a4fcd0c9 Gerrit-Change-Number: 59520 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/intel/txt: Allow platforms without FIT enable Intel TXT
by Michał Żygowski (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski. Michał Żygowski has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/59518 ) Change subject: security/intel/txt: Allow platforms without FIT enable Intel TXT ...................................................................... security/intel/txt: Allow platforms without FIT enable Intel TXT There is no real code or feature dependency on CPU_INTEL_FIRMWARE_INTERFACE_TABLE for Intel TXT. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I2858c8de9396449a0ee30837a98fab05570a6259 --- M src/security/intel/txt/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/59518/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2858c8de9396449a0ee30837a98fab05570a6259 Gerrit-Change-Number: 59518 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/intel/txt: Use common txt_reset_platform
by Michał Żygowski (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59517 to look at the new patch set (#2). Change subject: security/intel/txt: Use common txt_reset_platform ...................................................................... security/intel/txt: Use common txt_reset_platform Allow to set global reset bits on other platforms. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I561458044860ee5a26f7d61bcff1c407fa1533f2 --- M src/security/intel/txt/common.c M src/security/intel/txt/getsec.c M src/security/intel/txt/romstage.c M src/security/intel/txt/txt.h 4 files changed, 11 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/59517/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I561458044860ee5a26f7d61bcff1c407fa1533f2 Gerrit-Change-Number: 59517 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/intel/txt: Implement GETSEC PARAMETER dumping
by Michał Żygowski (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59516 to look at the new patch set (#2). Change subject: security/intel/txt: Implement GETSEC PARAMETER dumping ...................................................................... security/intel/txt: Implement GETSEC PARAMETER dumping Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I3b2c8337a8d86000a5b43788840d15146b662598 --- M src/security/intel/txt/common.c M src/security/intel/txt/logging.c M src/security/intel/txt/txt_register.h 3 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/59516/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b2c8337a8d86000a5b43788840d15146b662598 Gerrit-Change-Number: 59516 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/intel/txt: Remove unused region device
by Michał Żygowski (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59515 to look at the new patch set (#3). Change subject: security/intel/txt: Remove unused region device ...................................................................... security/intel/txt: Remove unused region device Region device is no longer used to locate BIOS ACM. Use new CBFS API to map and unmap the file. Using rdev_munmap on the uninitialized region device variable causes the platform to jump to a random adress. TEST=Dell OptiPlex 9010 does not raise #UD exception when Intel TXT is enabled, ACM SCHECK is successful Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I98afba35403d5d2cd9eeb7df6d1ca0171894e9d4 --- M src/security/intel/txt/common.c 1 file changed, 6 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/59515/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98afba35403d5d2cd9eeb7df6d1ca0171894e9d4 Gerrit-Change-Number: 59515 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/intel/txt: Correct reporting of chipset production fuse state
by Michał Żygowski (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59514 to look at the new patch set (#2). Change subject: security/intel/txt: Correct reporting of chipset production fuse state ...................................................................... security/intel/txt: Correct reporting of chipset production fuse state Implement the chipset production fuse state reporting as described in the Intel TXT Software Development Guide. TEST=Dell OptiPlex 9010 with i7-3770/Q77 reports the chipset is production fused Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ic86c5a9e1d162630a1cf61435d1014edabf104b0 --- M src/security/intel/txt/common.c M src/security/intel/txt/logging.c M src/security/intel/txt/txt.h 3 files changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/59514/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic86c5a9e1d162630a1cf61435d1014edabf104b0 Gerrit-Change-Number: 59514 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/sandybridge: Add support for DPR
by Michał Żygowski (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Michał Żygowski, Angel Pons. Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59512 to look at the new patch set (#2). Change subject: nb/intel/sandybridge: Add support for DPR ...................................................................... nb/intel/sandybridge: Add support for DPR Include DPR in the memory map calculations if enabled. DPR is required for Intel TXT support. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ia22e49ba58709acfa0afe0921aa71d83cc06c129 --- M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/sandybridge/northbridge.c 2 files changed, 43 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/59512/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia22e49ba58709acfa0afe0921aa71d83cc06c129 Gerrit-Change-Number: 59512 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021