coreboot-gerrit November 2021

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Change in coreboot[master]: drivers/analogix/anx7625: Fix edid_read()
by Yu-Ping Wu (Code Review) 22 Nov '21

22 Nov '21

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59540 ) Change subject: drivers/analogix/anx7625: Fix edid_read() ...................................................................... drivers/analogix/anx7625: Fix edid_read() The current implementations of edid_read() and segments_edid_read() have a few problems: 1. The type of variable `c` ic incorrect, not matching the return type of sp_tx_aux_rd(). In addition, the meaning of `c` is unknown. 2. It is pointless to do `cnt++` when sp_tx_aux_rd() fails. 3. These two functions ignore the return value of anx7625_reg_block_read(). 4. In segments_edid_read(), anx7625_reg_write() might return a positive value on failure. Fix all of the 4 issues, and modify the code to be closer to kernel's implementation (drivers/gpu/drm/bridge/analogix/anx7625.c). Note that, however, unlike in kernel, anx7625_reg_block_read() here doesn't return the number of bytes. On success, 0 is returned instead. In addition, change the return value to -1 for edid_read() and segments_edid_read() on failure. BUG=b:207055969 TEST=emerge-asurada coreboot BRANCH=none Change-Id: Ife9d7d97df2926b4581ba519a152c9efed8cd969 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/drivers/analogix/anx7625/anx7625.c 1 file changed, 26 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/59540/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 5fbcf20..638e793 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -558,34 +558,32 @@ static int edid_read(uint8_t bus, uint8_t offset, uint8_t *pblock_buf) { - uint8_t c, cnt = 0; + int ret, cnt; - c = 0; for (cnt = 0; cnt < 3; cnt++) { sp_tx_aux_wr(bus, offset); /* set I2C read com 0x01 mot = 0 and read 16 bytes */ - c = sp_tx_aux_rd(bus, 0xf1); + ret = sp_tx_aux_rd(bus, 0xf1); - if (c == 1) { + if (ret) { sp_tx_rst_aux(bus); ANXERROR("edid read failed, reset!\n"); - cnt++; } else { - anx7625_reg_block_read(bus, RX_P0_ADDR, - AP_AUX_BUFF_START, - MAX_DPCD_BUFFER_SIZE, pblock_buf); - return 0; + if (anx7625_reg_block_read(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, + MAX_DPCD_BUFFER_SIZE, + pblock_buf) == 0) + return 0; } } - return 1; + return -1; } static int segments_edid_read(uint8_t bus, uint8_t segment, uint8_t *buf, uint8_t offset) { - uint8_t c, cnt = 0; - int ret; + int ret, cnt; /* write address only */ ret = anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_ADDR_7_0, 0x30); @@ -599,7 +597,7 @@ /* data read */ ret |= anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_ADDR_7_0, 0x50); - if (ret < 0) { + if (ret) { ANXERROR("IO error: aux initial failed.\n"); return ret; } @@ -607,21 +605,21 @@ for (cnt = 0; cnt < 3; cnt++) { sp_tx_aux_wr(bus, offset); /* set I2C read com 0x01 mot = 0 and read 16 bytes */ - c = sp_tx_aux_rd(bus, 0xf1); + ret = sp_tx_aux_rd(bus, 0xf1); - if (c == 1) { - ret = sp_tx_rst_aux(bus); + if (ret) { + sp_tx_rst_aux(bus); ANXERROR("segment read failed, reset!\n"); - cnt++; } else { - ret = anx7625_reg_block_read(bus, RX_P0_ADDR, - AP_AUX_BUFF_START, - MAX_DPCD_BUFFER_SIZE, buf); - return ret; + if (anx7625_reg_block_read(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, + MAX_DPCD_BUFFER_SIZE, + buf) == 0) + return 0; } } - return ret; + return -1; } static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf, @@ -630,9 +628,7 @@ uint8_t offset, edid_pos; int count, blocks_num; uint8_t pblock_buf[MAX_DPCD_BUFFER_SIZE]; - uint8_t i; - uint8_t g_edid_break = 0; - int ret; + int i, ret, g_edid_break = 0; /* address initial */ ret = anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_ADDR_7_0, 0x50); @@ -656,10 +652,10 @@ case 1: for (i = 0; i < 8; i++) { offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; - g_edid_break = edid_read(bus, offset, - pblock_buf); + g_edid_break = !!edid_read(bus, offset, + pblock_buf); - if (g_edid_break == 1) + if (g_edid_break) break; if (offset <= size - MAX_DPCD_BUFFER_SIZE) @@ -677,11 +673,11 @@ edid_pos = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; - if (g_edid_break == 1) + if (g_edid_break) break; segments_edid_read(bus, count / 2, - pblock_buf, offset); + pblock_buf, offset); if (edid_pos <= size - MAX_DPCD_BUFFER_SIZE) memcpy(&pedid_blocks_buf[edid_pos], pblock_buf, -- To view, visit https://review.coreboot.org/c/coreboot/+/59540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife9d7d97df2926b4581ba519a152c9efed8cd969 Gerrit-Change-Number: 59540 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/analogix/anx7625: Fix return code handling
by Yu-Ping Wu (Code Review) 22 Nov '21

22 Nov '21

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59539 ) Change subject: drivers/analogix/anx7625: Fix return code handling ...................................................................... drivers/analogix/anx7625: Fix return code handling On some platforms (rockchip, mediatek), platform_i2c_transfer() might return a positive error code, and so are i2c_readb() and i2c_writeb(). Currently the analogix driver incorrectly assumes the error code is always negative. Therefore, fix the return code handling in functions anx7625_reg_*(), and return -1 from them. BUG=b:207055969 TEST=emerge-asurada coreboot BRANCH=none Change-Id: I955b9aae11e20d75fac414d15714330e364dad2f Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/drivers/analogix/anx7625/anx7625.c 1 file changed, 22 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/59539/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 11e9ed1..5fbcf20 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -54,9 +54,12 @@ } ret = i2c_writeb(bus, saddr, offset, 0x00); - if (ret < 0) - ANXERROR("Failed to access %#x:%#x\n", saddr, offset); - return ret; + if (ret) { + ANXERROR("Failed to access %#x:%#x, ret=%#x\n", saddr, offset, + ret); + return -1; + } + return 0; } static int anx7625_reg_read(uint8_t bus, uint8_t saddr, uint8_t offset, @@ -66,9 +69,10 @@ i2c_access_workaround(bus, saddr); ret = i2c_readb(bus, saddr, offset, val); - if (ret < 0) { - ANXERROR("Failed to read i2c reg=%#x:%#x\n", saddr, offset); - return ret; + if (ret) { + ANXERROR("Failed to read i2c reg=%#x:%#x, ret=%#x\n", saddr, + offset, ret); + return -1; } return *val; } @@ -80,10 +84,12 @@ i2c_access_workaround(bus, saddr); ret = i2c_read_bytes(bus, saddr, reg_addr, buf, len); - if (ret < 0) - ANXERROR("Failed to read i2c block=%#x:%#x[len=%#x]\n", saddr, - reg_addr, len); - return ret; + if (ret) { + ANXERROR("Failed to read i2c block=%#x:%#x[len=%#x], ret=%#x\n", + saddr, reg_addr, len, ret); + return -1; + } + return 0; } static int anx7625_reg_write(uint8_t bus, uint8_t saddr, uint8_t reg_addr, @@ -93,10 +99,13 @@ i2c_access_workaround(bus, saddr); ret = i2c_writeb(bus, saddr, reg_addr, reg_val); - if (ret < 0) - ANXERROR("Failed to write i2c id=%#x:%#x\n", saddr, reg_addr); + if (ret) { + ANXERROR("Failed to write i2c id=%#x:%#x, ret=%#x\n", saddr, + reg_addr, ret); + return -1; + } - return ret; + return 0; } static int anx7625_write_or(uint8_t bus, uint8_t saddr, uint8_t offset, -- To view, visit https://review.coreboot.org/c/coreboot/+/59539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955b9aae11e20d75fac414d15714330e364dad2f Gerrit-Change-Number: 59539 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/thermal: Refactor thermal block to improve reusability
by Angel Pons (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59509 ) Change subject: soc/intel/common/thermal: Refactor thermal block to improve reusability ...................................................................... Patch Set 4: Code-Review+1 (2 comments) File src/soc/intel/common/block/include/intelblocks/thermal.h: https://review.coreboot.org/c/coreboot/+/59509/comment/85d5d635_83ac9863 PS4, Line 20: #define GET_LTT_VALUE(x) ((x + 10) << 20 | (x + 5) << 10 | x) Please wrap `x` in parentheses to avoid operation order problems: #define GET_LTT_VALUE(x) (((x) + 10) << 20 | ((x) + 5) << 10 | (x)) File src/soc/intel/common/block/thermal/Kconfig: https://review.coreboot.org/c/coreboot/+/59509/comment/76b4da14_bfd2a61c PS4, Line 7: config SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV : bool : default n : select SOC_INTEL_COMMON_BLOCK_THERMAL : help : This option allows to configure PCH thermal registers using Thermal PCI device : for chipsets till Ice Lake PCH. : : config SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC : bool : default n : select SOC_INTEL_COMMON_BLOCK_THERMAL : help : This option allows to configure PCH thermal registers using PMC PWRMBASE : for chipsets since Tiger Lake PCH. Would be good to make these two Kconfig options mutually exclusive. I haven't tested this, but here's an idea: config SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV bool default n depends on !SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC select SOC_INTEL_COMMON_BLOCK_THERMAL help This option allows to configure PCH thermal registers using Thermal PCI device for chipsets till Ice Lake PCH. config SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC bool default n depends on !SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV select SOC_INTEL_COMMON_BLOCK_THERMAL help This option allows to configure PCH thermal registers using PMC PWRMBASE for chipsets since Tiger Lake PCH. -- To view, visit https://review.coreboot.org/c/coreboot/+/59509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Gerrit-Change-Number: 59509 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 08:59:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h`
by Angel Pons (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59510 ) Change subject: soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h` ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59510/comment/4f67b481_7847713c PS2, Line 7: Remove unused header `thermal.h` I think the commit summary is confusing, as this change doesn't remove any files. Instead, I would've used: Remove unnecessary `thermal.h` include I know this change has already been submitted, but I still want to point this out for future changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/59510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9ac0ffb352686af22cc9d11b61f904238eef278 Gerrit-Change-Number: 59510 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 08:54:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add set batteryinfo support for ec
by Sumeet R Pawnikar (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Tim Wawrzynczak. Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59538 ) Change subject: mb/google/brya: Add set batteryinfo support for ec ...................................................................... mb/google/brya: Add set batteryinfo support for ec Add set batteryinfo support under acpi for ec for Alder Lake based brya system. BUG=b:206057712 BRANCH=None TEST=Build and test on brya system Change-Id: Ic230671d95233f86afef1fc45a4b8f2aa613f7f7 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/ec.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59538/1 diff --git a/src/mainboard/google/brya/ec.c b/src/mainboard/google/brya/ec.c index eb8c387..df686c6 100644 --- a/src/mainboard/google/brya/ec.c +++ b/src/mainboard/google/brya/ec.c @@ -24,4 +24,7 @@ /* Get the powerinfo config details */ ret = google_chromeec_get_powerinfo_config(); + + /* Set the batteryinfo config details */ + google_chromeec_set_batteryinfo_config(ISL9241_BC12_MIN_VOLTAGE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/59538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic230671d95233f86afef1fc45a4b8f2aa613f7f7 Gerrit-Change-Number: 59538 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Add get powerinfo support for ec
by Sumeet R Pawnikar (Code Review) 22 Nov '21

22 Nov '21

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59537 ) Change subject: mb/google/brya: Add get powerinfo support for ec ...................................................................... mb/google/brya: Add get powerinfo support for ec Add get powerinfo support under acpi for ec for Alder Lake based brya system. BUG=b:205928013 BRANCH=None TEST=Build and test on brya system Change-Id: I7e7dc64fd1602180230f3e5fd3c13558a37f3f07 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/ec.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/59537/1 diff --git a/src/mainboard/google/brya/ec.c b/src/mainboard/google/brya/ec.c index 6d0c426..eb8c387 100644 --- a/src/mainboard/google/brya/ec.c +++ b/src/mainboard/google/brya/ec.c @@ -4,10 +4,12 @@ #include <console/console.h> #include <ec/ec.h> #include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> #include <variant/ec.h> void mainboard_ec_init(void) { + int ret; static const struct google_chromeec_event_info info = { .log_events = MAINBOARD_EC_LOG_EVENTS, .sci_events = MAINBOARD_EC_SCI_EVENTS, @@ -19,4 +21,7 @@ printk(BIOS_ERR, "mainboard: EC init\n"); google_chromeec_events_init(&info, acpi_is_wakeup_s3()); + + /* Get the powerinfo config details */ + ret = google_chromeec_get_powerinfo_config(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/59537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e7dc64fd1602180230f3e5fd3c13558a37f3f07 Gerrit-Change-Number: 59537 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads
by Angel Pons (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Evgeny Zinoviev, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59527 ) Change subject: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads ...................................................................... Patch Set 2: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59527/comment/c8aca44f_df64aee1 PS2, Line 7: Sandy Bridge Strictly speaking, this should be `Cougar Point`, the PCH. It's possible [1] to use Ivy Bridge CPUs on these mainboards. [1]: Even though it's very complicated, it's possible to replace BGA CPUs. https://review.coreboot.org/c/coreboot/+/59527/comment/87636916_f19517dc PS2, Line 12: 0793afe9 commit 0793afe9 (mb/lenovo/x220: disable ME) https://review.coreboot.org/c/coreboot/+/59527/comment/3dcc2342_90462100 PS2, Line 13: today With which Linux kernel version? https://review.coreboot.org/c/coreboot/+/59527/comment/c72e975c_4fe4ed10 PS2, Line 15: Also: : - it breaks the me_disable feature, : - we already have a Kconfig option to hide MEI in case of errors, : - it will be hidden on disabled, recovery, firmware update paths anyway. I'd convert this list of reasons into a paragraph. -- To view, visit https://review.coreboot.org/c/coreboot/+/59527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a Gerrit-Change-Number: 59527 Gerrit-PatchSet: 2 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 08:46:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
by Ravindra (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Ravindra, Patrick Rudolph. Ravindra has uploaded a new patch set (#12) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/55364 ) Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init ...................................................................... soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init The patch enables cse_fw_sync() before DRAM initialization. BUG=b:175516533 TEST=Dependency with CSE Litev16.0.15.1545 integration Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 3 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/55364/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/55364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Gerrit-Change-Number: 55364 Gerrit-PatchSet: 12 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads
by Paul Menzel (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Evgeny Zinoviev, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59527 ) Change subject: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59527/comment/106296f7_7b49d261 PS2, Line 12: 0793afe9 commit 0793afe9 (mb/lenovo/x220: disable ME) -- To view, visit https://review.coreboot.org/c/coreboot/+/59527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a Gerrit-Change-Number: 59527 Gerrit-PatchSet: 2 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 08:39:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add set batteryinfo support
by Sumeet R Pawnikar (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59262 ) Change subject: soc/intel/alderlake: Add set batteryinfo support ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: moving this change to specific system/board brya -- To view, visit https://review.coreboot.org/c/coreboot/+/59262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02350a2c8e3dd4cdb061a6976f44e4b839a305a4 Gerrit-Change-Number: 59262 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 08:17:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021