Hello Felix Singer, build bot (Jenkins), David Hendricks,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59229
to look at the new patch set (#2).
Change subject: Documentation: Add warning about "private" changes on Gerrit
......................................................................
Documentation: Add warning about "private" changes on Gerrit
Private changes on Gerrit are a tricky beast in that they're well hidden
in the UI and a few other places but still reachable under certain
circumstances.
Change-Id: I1c8c6cccfd023bc1d839dc5d9544204c88f89c7e
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M Documentation/getting_started/gerrit_guidelines.md
M Documentation/tutorial/part2.md
2 files changed, 7 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/59229/2
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Change subject: mb/google/dedede/var/beetley: Enable Wifi SAR for beetley
......................................................................
Removed reviewer build bot (Jenkins) with the following votes:
* Verified+1 by build bot (Jenkins) <no-reply(a)coreboot.org>
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59516 )
Change subject: security/intel/txt: Implement GETSEC PARAMETER dumping
......................................................................
Patch Set 3:
(2 comments)
File src/security/intel/txt/logging.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134003):
https://review.coreboot.org/c/coreboot/+/59516/comment/280b5b08_c19a4562
PS3, Line 253: if (txt_feature_flags & GETSEC_PARAMS_TXT_EXT_CRTM_SUPPORT) {
braces {} are not necessary for any arm of this statement
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134003):
https://review.coreboot.org/c/coreboot/+/59516/comment/9c5f08b1_7891af07
PS3, Line 259: if (txt_feature_flags & GETSEC_PARAMS_TXT_EXT_MACHINE_CHECK) {
braces {} are not necessary for any arm of this statement
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I3b2c8337a8d86000a5b43788840d15146b662598
Gerrit-Change-Number: 59516
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Change subject: security/intel/txt: Correct reporting of chipset production fuse state
......................................................................
Patch Set 3:
(1 comment)
File src/security/intel/txt/common.c:
https://review.coreboot.org/c/coreboot/+/59514/comment/8bd8bec9_85aaa33a
PS2, Line 155: reg = read64((void *)TXT_VER_QPIIF);
> this seems to be 32bit register as well
Done
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Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59514
to look at the new patch set (#3).
Change subject: security/intel/txt: Correct reporting of chipset production fuse state
......................................................................
security/intel/txt: Correct reporting of chipset production fuse state
Implement the chipset production fuse state reporting as described in
the Intel TXT Software Development Guide.
TEST=Dell OptiPlex 9010 with i7-3770/Q77 reports the chipset is
production fused
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Ic86c5a9e1d162630a1cf61435d1014edabf104b0
---
M src/security/intel/txt/common.c
M src/security/intel/txt/logging.c
M src/security/intel/txt/txt.h
3 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/59514/3
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59523 )
Change subject: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT
......................................................................
Patch Set 2:
(1 comment)
File src/northbridge/intel/sandybridge/romstage.c:
https://review.coreboot.org/c/coreboot/+/59523/comment/c7a0d5f4_54679108
PS2, Line 78: #if CONFIG(INTEL_TXT)
> use if(CONFIG(INTEL_TXT)) {
But then if INTEL_TXT is not selected in the configuration, the intel_txt_romstage_init will not have any implementation. Are you fine with an empty __weak intel_txt_romstage_init in this file?
Or alternatively we may always compile the romstage part of TXT driver. If MLE will not set up, we should not hit the situation when there is a TXT wake error and TPM establishment asserted. ACM doesn't have to be included because there would be no need for SCLEAN if I am deducting correctly.
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Change subject: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59521/comment/59c51990_f4b34c6c
PS2, Line 10: memory on a TXT enabled platform. Previosuly on Sandybridge raminit the
> this MSR is actually written in init_dram_ddr3(). […]
Since TXT is optional, we would still need to have this fragment just in case the memory controller would be locked. Having it in the TXT driver allows to use it in a controlled manner, i.e. only when TXT is checked to be supported by the chipset and CPU. By the way, this MSR should generate #GP when CPU or chipset is not TXT capable, we do not guard this in src/northbridge/intel/sandybridge/raminit.c. have you experienced such issues?
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Hello build bot (Jenkins), Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59527
to look at the new patch set (#4).
Change subject: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads
......................................................................
mb/lenovo: Enable MEI on Sandy Bridge ThinkPads
It was already enabled on T520 and L520, but disabled on X220, T420 and
T420s.
On X220, it was disabled by commit 0793afe9 (mb/lenovo/x220: disable ME).
I can't reproduce those issues today on linux 4.4 and linux 5.13.
Also, it breaks the me_disable feature, we already have a Kconfig option
to hide MEI in case of errors, and it will be hidden on disabled,
recovery, firmware update paths anyway.
Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
M src/mainboard/lenovo/t420/devicetree.cb
M src/mainboard/lenovo/t420s/devicetree.cb
M src/mainboard/lenovo/x220/devicetree.cb
3 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/59527/4
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