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Change subject: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed
......................................................................
Patch Set 3:
(2 comments)
File src/security/intel/txt/romstage.c:
https://review.coreboot.org/c/coreboot/+/59521/comment/62bc46a0_8a206c93
PS3, Line 134: } else if (!establishment) {
> If TPM establishment is asserted but there's no TXT wake error, this function won't unlock memory.
Right, it should be done regardless of TPM establishment.
https://review.coreboot.org/c/coreboot/+/59521/comment/79ba777d_dc63d71c
PS3, Line 138: wrmsr(TXT_UNLOCK_MEMORY_MSR, msr);
> Doesn't native raminit already do this? […]
Yes it does, we have a separate discussion in this patch. I am not sure though if the MSR should be always written. You could advise there how to approach the code duplication.
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Change subject: mb/prodrive/hermes: Rename "internal audio" setting
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Patch Set 1: Code-Review+2
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Change subject: drivers/analogix/anx7625: Fix return code handling
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59539/comment/71cb6d42_4d0e2471
PS1, Line 13: anx7625_reg_*(), and return -1 from them.
… and log the received return code.
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Change subject: mb/prodrive/hermes: Rename "internal audio" setting
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Patch Set 1: Code-Review+1
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Change subject: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT
......................................................................
Patch Set 3:
(4 comments)
File src/northbridge/intel/sandybridge/romstage.c:
https://review.coreboot.org/c/coreboot/+/59523/comment/1e9b79ca_3e7ebb26
PS2, Line 78: #if CONFIG(INTEL_TXT)
> But then if INTEL_TXT is not selected in the configuration, the intel_txt_romstage_init will not hav […]
Please don't add weak symbols. Just look at what Haswell code does. Yes, it doesn't configure DPR, it relies on a patched MRC.bin doing it. I didn't think of programming and locking the DPR register before running MRC.
File src/northbridge/intel/sandybridge/romstage.c:
https://review.coreboot.org/c/coreboot/+/59523/comment/a47ddcde_321f6d87
PS3, Line 28: #if CONFIG(INTEL_TXT)
Is this guard needed?
https://review.coreboot.org/c/coreboot/+/59523/comment/1c13da94_b4cc919b
PS3, Line 35: /* 3 MiB should be enough */
I'd omit this comment.
https://review.coreboot.org/c/coreboot/+/59523/comment/5bfadf9b_f11d7990
PS3, Line 36: pci_write_config32(HOST_BRIDGE, DPR, dpr.raw);
Where does dpr.top come from?
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Change subject: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59521/comment/b05a758f_d67dccb0
PS2, Line 10: memory on a TXT enabled platform. Previosuly on Sandybridge raminit the
> Since TXT is optional, we would still need to have this fragment just in case the memory controller […]
I'm pretty sure the MSR always needs to be written.
Commit Message:
https://review.coreboot.org/c/coreboot/+/59521/comment/7125cba7_73a86dab
PS3, Line 10: Previosuly
typo: Previously
File src/security/intel/txt/romstage.c:
https://review.coreboot.org/c/coreboot/+/59521/comment/5d22eaa2_96397c09
PS3, Line 134: } else if (!establishment) {
If TPM establishment is asserted but there's no TXT wake error, this function won't unlock memory.
https://review.coreboot.org/c/coreboot/+/59521/comment/91b925e5_56031c01
PS3, Line 138: wrmsr(TXT_UNLOCK_MEMORY_MSR, msr);
Doesn't native raminit already do this?
src/northbridge/intel/sandybridge/raminit.c: wrmsr(0x2e6, (msr_t) { .lo = 0, .hi = 0 });
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Change subject: configs: Add config for Prodrive Hermes
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Patch Set 2: Code-Review+1
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