coreboot-gerrit November 2021

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: use bit definitions for masks
by Marshall Dawson (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59593 ) Change subject: soc/amd/common/block/include/gpio_defs: use bit definitions for masks ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bc9e1cecf2f063b42de3f8875fee421dd256648 Gerrit-Change-Number: 59593 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 24 Nov 2021 17:11:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: remove unneeded line break
by Marshall Dawson (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59592 ) Change subject: soc/amd/common/block/include/gpio_defs: remove unneeded line break ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b9c3885259b9acf0539eed14e23fbbb0deccea7 Gerrit-Change-Number: 59592 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 24 Nov 2021 17:10:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Enable DRIVERS_GENESYSLOGIC_GL9750
by Felix Held (Code Review) 24 Nov '21

24 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59579 ) Change subject: mb/google/brya/var/gimble: Enable DRIVERS_GENESYSLOGIC_GL9750 ...................................................................... mb/google/brya/var/gimble: Enable DRIVERS_GENESYSLOGIC_GL9750 Enable DRIVERS_GENESYSLOGIC_GL9750 support for Gimble. BUG=b:206014046 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Change-Id: Ifc490e6e081b6a8534656417603d2916c3edcb05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59579 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Mark Hsieh: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 11f9b69..3a43b9c 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -28,6 +28,7 @@ select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_DSM_CALIB if CHROMEOS select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_I2C_MAX98390 config BOARD_GOOGLE_REDRIX -- To view, visit https://review.coreboot.org/c/coreboot/+/59579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc490e6e081b6a8534656417603d2916c3edcb05 Gerrit-Change-Number: 59579 Gerrit-PatchSet: 2 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: drop 8k pullup define
by Marshall Dawson (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59591 ) Change subject: soc/amd/common/block/include/gpio_defs: drop 8k pullup define ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59591/comment/646b8fc8_b7484423 PS1, Line 9: reserved in all SoCs I believe Picasso (#55570) defines it but there must be no system using it. -- To view, visit https://review.coreboot.org/c/coreboot/+/59591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf2d4eec7a13e558c75d7edea343b876909a5b33 Gerrit-Change-Number: 59591 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 24 Nov 2021 17:09:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: update memory settings
by Tim Wawrzynczak (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Kevin Chiu, YH Lin, Nick Vaccaro, Shon Wang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59334 ) Change subject: mb/google/brya/var/vell: update memory settings ...................................................................... Patch Set 6: Code-Review+1 (3 comments) File src/mainboard/google/brya/variants/vell/memory.c: https://review.coreboot.org/c/coreboot/+/59334/comment/cf0dd925_43c77328 PS5, Line 7: __weak > remove if you want to override Done https://review.coreboot.org/c/coreboot/+/59334/comment/424c24e8_986c7548 PS5, Line 26: __weak > remove if you want to override Done File src/mainboard/google/brya/variants/vell/memory.c: https://review.coreboot.org/c/coreboot/+/59334/comment/0afb550a_087ced9c PS6, Line 16: 40, 30, 30, 30, 30 I believe Intel's recommended values for LP5 are `40, 36, 35, 35, 35` -- To view, visit https://review.coreboot.org/c/coreboot/+/59334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Gerrit-Change-Number: 59334 Gerrit-PatchSet: 6 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 24 Nov 2021 17:09:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/include/acpi: fix reference to main acpi include
by Felix Held (Code Review) 24 Nov '21

24 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59587 ) Change subject: soc/amd/common/block/include/acpi: fix reference to main acpi include ...................................................................... soc/amd/common/block/include/acpi: fix reference to main acpi include commit e0844636aca974449c7257e846ec816db683d0b9 (acpi: Move ACPI table support out of arch/x86 (2/5)) moved the main acpi header file from arch/x86/include/acpi/acpi.h to include/acpi/acpi.h, so change the comment in here to point to the current location. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5fddd1cd5eefd83816b1c966b5c7edf53eb2486d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59587 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/acpi.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 550b7d7..e87fcdb 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -12,7 +12,7 @@ #define MMIO_ACPI_PM1_STS 0x00 #define MMIO_ACPI_PM1_EN 0x02 #define MMIO_ACPI_PM1_CNT_BLK 0x04 - /* sleep types defined in arch/x86/include/acpi/acpi.h */ + /* sleep types defined in include/acpi/acpi.h */ #define ACPI_PM1_CNT_SCIEN BIT(0) #define MMIO_ACPI_PM_TMR_BLK 0x08 #define MMIO_ACPI_CPU_CONTROL 0x0c -- To view, visit https://review.coreboot.org/c/coreboot/+/59587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fddd1cd5eefd83816b1c966b5c7edf53eb2486d Gerrit-Change-Number: 59587 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: add GPIO IRQ status registers
by Felix Held (Code Review) 24 Nov '21

24 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59590 ) Change subject: soc/amd/common/block/include/gpio_defs: add GPIO IRQ status registers ...................................................................... soc/amd/common/block/include/gpio_defs: add GPIO IRQ status registers Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I585691038690f1d6855ab09f1ca5791a18cfdbfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/59590 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index db90211..757e0f2 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -10,6 +10,8 @@ #define GPIO_WAKE_STAT_0 0x2f0 #define GPIO_WAKE_STAT_1 0x2f4 +#define GPIO_IRQ_STAT_0 0x2f8 +#define GPIO_IRQ_STAT_1 0x2fc #define GPIO_PIN_IN (1 << 0) /* for byte access */ #define GPIO_PIN_OUT (1 << 6) /* for byte access */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585691038690f1d6855ab09f1ca5791a18cfdbfe Gerrit-Change-Number: 59590 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add ADLP 4+4+2 power configurations
by Tim Wawrzynczak (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Paul Menzel, Curtis Chen, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59483 ) Change subject: soc/intel/alderlake: Add ADLP 4+4+2 power configurations ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59483/comment/0ff6b3a2_03c5d8db PS3, Line 9: Map exist PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 442 : sku power related settings. > commit msgs are 72 characters wide please Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731 Gerrit-Change-Number: 59483 Gerrit-PatchSet: 5 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 24 Nov 2021 17:05:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add ADLP 4+4+2 power configurations
by Tim Wawrzynczak (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Paul Menzel, Curtis Chen, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59483 ) Change subject: soc/intel/alderlake: Add ADLP 4+4+2 power configurations ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59483/comment/06935260_e4c903af PS3, Line 9: ADLP > `Map existing PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADL-P 4+4+2 configuration` […] Done https://review.coreboot.org/c/coreboot/+/59483/comment/9df1f8bd_a1448dd4 PS3, Line 10: sku > SKU Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731 Gerrit-Change-Number: 59483 Gerrit-PatchSet: 5 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 24 Nov 2021 17:05:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: use lower case in hex numbers
by Felix Held (Code Review) 24 Nov '21

24 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59589 ) Change subject: soc/amd/common/block/include/gpio_defs: use lower case in hex numbers ...................................................................... soc/amd/common/block/include/gpio_defs: use lower case in hex numbers Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Icb1c7b243f655225347ba2a78c80e6e8653e8cda Reviewed-on: https://review.coreboot.org/c/coreboot/+/59589 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 8545037..db90211 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -3,13 +3,13 @@ #ifndef AMD_BLOCK_GPIO_DEFS_H #define AMD_BLOCK_GPIO_DEFS_H -#define GPIO_MASTER_SWITCH 0xFC +#define GPIO_MASTER_SWITCH 0xfc #define GPIO_MASK_STS_EN BIT(28) #define GPIO_INTERRUPT_EN BIT(30) #define GPIO_WAKE_EN BIT(31) -#define GPIO_WAKE_STAT_0 0x2F0 -#define GPIO_WAKE_STAT_1 0x2F4 +#define GPIO_WAKE_STAT_0 0x2f0 +#define GPIO_WAKE_STAT_1 0x2f4 #define GPIO_PIN_IN (1 << 0) /* for byte access */ #define GPIO_PIN_OUT (1 << 6) /* for byte access */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb1c7b243f655225347ba2a78c80e6e8653e8cda Gerrit-Change-Number: 59589 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021