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Change subject: guybrush: add RO_GSCVD area to FMAP
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> what is the process of merging changes in this tree, I don't remember any more.
For upstream tree, it is manually submitted after 24 hours of uploading the latest patchset - provided all comments are resolved.
For downstream tree, there is a downstreaming service with some manual intervention. `Cq-Depend:` is to meet the dependencies in the downstream tree. It can be added in the upstream CL though so that the downstreamers are aware of it.
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Change subject: timestamp: Add new helper functions
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51445/comment/296b3e35_706cd631
PS3, Line 7: Add helper fucntions
> Subrata, the problem is that you're flipping the sign on the negative timestamps in https://review.coreboot.org/c/coreboot/+/59555/2/util/cbmem/cbmem.c#618,
I agree with this feedback.
> and you shouldn't. If you don't then the sorting will happen exactly as Angel said, 944 first, then in order up to 947, then timestamp 0, then the positive ones. That is what we want.
Ahh, got it. yes, this is the order what we want.
>
> Please see my comment on CB:59555, it should really just take a couple of lines to do this, not a second sort and all the extra stuff you're doing. The final output should be
>
> 944:CSE sent 'Boot Stall Done' to PMC 0
> 945:CSE started to handle ICC configuration 766,000 (766,000)
> 946:CSE sent 'Host BIOS Prep Done' to PMC 771,000 (5,000)
> 947:CSE received 'CPU Reset Done Ack sent' from PMC 778,000 (7,000)
> 0:1st timestamp 1,074,000 (296,000)
>
> (We could also choose not to set the first timestamp to 0 and print the numbers negative as they are if you prefer that... but I think that would be more confusing than helpful.)
true, adding negative would have been nice but might create confusion. Additionally, we want to accommodate the pre-cpu reset time as well in total FW booting time till kernel. For sure we don't want to eliminate those while calculating the final time.
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Change subject: guybrush: add RO_GSCVD area to FMAP
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57864/comment/4ce6b2e7_3e85efe8
PS2, Line 25:
> Cq-Depend: TBD […]
Ack
Patchset:
PS2:
what is the process of merging changes in this tree, I don't remember any more.
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Change subject: guybrush: add RO_GSCVD area to FMAP
......................................................................
Patch Set 2: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57864/comment/ce8df7cd_28a5c420
PS2, Line 25:
Cq-Depend: TBD
Reason: Since signed PSP verstage has a snapshot of different FMAP, it will fail to boot. This change is good to land upstream. For downstream, we have to sign the PSP verstage with the updated FMAP and land it along with the downstream CL.
Patchset:
PS2:
Adding Raul/Rob for visibility.
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Change subject: timestamp: Add new helper functions
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51445/comment/755688be_b048bb57
PS3, Line 7: Add helper fucntions
> > > Thanks Angel and Julius for your suggestion. […]
Subrata, the problem is that you're flipping the sign on the negative timestamps in https://review.coreboot.org/c/coreboot/+/59555/2/util/cbmem/cbmem.c#618, and you shouldn't. If you don't then the sorting will happen exactly as Angel said, 944 first, then in order up to 947, then timestamp 0, then the positive ones. That is what we want.
Please see my comment on CB:59555, it should really just take a couple of lines to do this, not a second sort and all the extra stuff you're doing. The final output should be
944:CSE sent 'Boot Stall Done' to PMC 0
945:CSE started to handle ICC configuration 766,000 (766,000)
946:CSE sent 'Host BIOS Prep Done' to PMC 771,000 (5,000)
947:CSE received 'CPU Reset Done Ack sent' from PMC 778,000 (7,000)
0:1st timestamp 1,074,000 (296,000)
(We could also choose not to set the first timestamp to 0 and print the numbers negative as they are if you prefer that... but I think that would be more confusing than helpful.)
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Change subject: soc/amd/common/block/include/gpio_defs: drop 8k pullup define
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59591/comment/f3df8f87_a726790f
PS1, Line 9: reserved in all SoCs
> turns out that version 3.14 of #55570 had this bit defined, but version 3.16 and 3. […]
the Cezanne PPR has reset values for that bit and it's 0, so this patch shouldn't change the value that will end up in that register at bit 19. the other PPRs/BKDGs only listed the bit as reserved with no reset value being specified
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