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Change subject: soc/amd/common/acpi/gpio_bank_lib: drop unused methods
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Patch Set 1: Code-Review+2
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Change subject: ec/google/chromeec: Add powerinfo support
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Patch Set 3:
(1 comment)
File src/ec/google/chromeec/ec.c:
https://review.coreboot.org/c/coreboot/+/59189/comment/f9468c43_cb6a8f40
PS3, Line 1848: void
shouldn't `resp` be an argument so you can actually get the data back from the host command?
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Change subject: soc/amd/common/block/include/gpio_defs: drop 8k pullup define
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59591/comment/07142121_5cf8135a
PS1, Line 9: reserved in all SoCs
> re-checked and bit 19 is marked as reserved in all GPIO register bank definitions: 19 Reserved. […]
turns out that version 3.14 of #55570 had this bit defined, but version 3.16 and 3.18 have it marked as reserved. i checked recent versions of all PPRs/BKDGs and all had the bit defined as reserved
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Change subject: soc/amd/common/block/include/gpio_defs: drop unused GPIO_PIN_IN/OUT
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Change subject: soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_ACPI_GPIO
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Change subject: soc/amd/common/block/include/gpio_defs: drop 8k pullup define
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Patch Set 1:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/59591/comment/1e719b32_e063d1e6
PS1, Line 9: reserved in all SoCs
> I believe Picasso (#55570) defines it but there must be no system using it.
re-checked and bit 19 is marked as reserved in all GPIO register bank definitions: 19 Reserved.
iirc i checked #52740 for mullins, #55072 for stoneyridge, #55570 for picasso and #56569 for cezanne
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Change subject: soc/amd/common/block/include/gpio_defs: de-duplicate pin status bit defs
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Change subject: mb/google/brya/var/vell: update gpio override
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Patch Set 8:
(3 comments)
File src/mainboard/google/brya/variants/vell/gpio.c:
https://review.coreboot.org/c/coreboot/+/59305/comment/e27f412f_6f438a49
PS8, Line 10: /* A6 : ESPI_ALERT1# ==> ESPI_ALERT1 */
: PAD_CFG_GPI(GPP_A6, NONE, DEEP),
I don't think we use ESPI Alert1 on chrome EC platforms?
https://review.coreboot.org/c/coreboot/+/59305/comment/bb128d9b_a8a75ac0
PS8, Line 17: /* B2 : VRALERT# ==> RGB_RST_ODL */
: PAD_CFG_GPI(GPP_B2, NONE, DEEP),
Is this used to reset something or to read the reset state? It is programmed as an input here, so I am guessing it is for reading the reset state?
https://review.coreboot.org/c/coreboot/+/59305/comment/035cceb3_cdd28ecb
PS8, Line 151:
You probably want to consider having a romstage GPIO table too, for the SSD PERST# deassertion, e.g.:
```
static const struct pad_config romstage_gpio_table[] = {
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 1, DEEP),
};
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}
```
otherwise the FSP may not find anything downstream of the root port and thus disable that root port.
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Change subject: soc/amd/common/block/include/gpio_defs: drop duplicate wake bit defs
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