coreboot-gerrit November 2021

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Change in coreboot[master]: dptf: Add support for one more temperature sensor
by Arthur Heymans (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Lance Zhao, Tim Wawrzynczak, Sumeet R Pawnikar, Nick Vaccaro, Scott Chao, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59632 ) Change subject: dptf: Add support for one more temperature sensor ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf9666bade23b9bb4f740c6c4df6ecf5227cfb45 Gerrit-Change-Number: 59632 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 24 Nov 2021 16:55:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso,stoneyridge/acpi: use define for RTC_DATE_ALARM
by Marshall Dawson (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59586 ) Change subject: soc/amd/picasso,stoneyridge/acpi: use define for RTC_DATE_ALARM ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa4b3b3cdb161670128b284a3396fc5a85545608 Gerrit-Change-Number: 59586 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 24 Nov 2021 16:54:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Support 5 temperature sensors
by Tim Wawrzynczak (Code Review) 24 Nov '21

24 Nov '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59633 ) Change subject: ec/google/chromeec: Support 5 temperature sensors ...................................................................... ec/google/chromeec: Support 5 temperature sensors Some boards with the chrome EC will need to support more than 4 temperature sensors, so modify the number of TSRs supported when generating the ACPI code. Note that the EC memory map already has support for up to 16 TSRs, so no change is required on the EC side. BUG=b:207585491 TEST=with previous patch and some test data in brya0 overridetree.cb, dump the SSDT and verify that all of the existing Methods for TSR0-TSR3 are also added for TSR4, as well as all Notify, etc. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Id002230bc872b0f818b0bf2b87987298189c973d --- M src/ec/google/chromeec/ec_dptf_helpers.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/59633/1 diff --git a/src/ec/google/chromeec/ec_dptf_helpers.c b/src/ec/google/chromeec/ec_dptf_helpers.c index 631f16e..94b13fb 100644 --- a/src/ec/google/chromeec/ec_dptf_helpers.c +++ b/src/ec/google/chromeec/ec_dptf_helpers.c @@ -265,7 +265,7 @@ /* Local0 = ToInteger(Arg0) */ acpigen_write_to_integer(ARG0_OP, LOCAL0_OP); - for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) { + for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) { snprintf(name, sizeof(name), "^TSR%1d", i); acpigen_write_if_lequal_op_int(LOCAL0_OP, i); acpigen_notify(name, THERMAL_EVENT); @@ -277,7 +277,7 @@ /* TPET */ acpigen_write_method("TPET", 0); - for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) { + for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) { snprintf(name, sizeof(name), "^TSR%1d", i); acpigen_notify(name, TRIP_POINTS_CHANGED_EVENT); } @@ -355,6 +355,6 @@ write_charger_methods(ec); write_fan_methods(ec); - for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) + for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) write_thermal_methods(ec, p, i); } -- To view, visit https://review.coreboot.org/c/coreboot/+/59633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id002230bc872b0f818b0bf2b87987298189c973d Gerrit-Change-Number: 59633 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: dptf: Add support for one more temperature sensor
by Tim Wawrzynczak (Code Review) 24 Nov '21

24 Nov '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59632 ) Change subject: dptf: Add support for one more temperature sensor ...................................................................... dptf: Add support for one more temperature sensor Some boards may use more than 4 temperature sensors for DPTF thermal control, so this patch adds support for one more temperature sensor. BUG=b:207585491 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ibf9666bade23b9bb4f740c6c4df6ecf5227cfb45 --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/dptf.c M src/include/acpi/acpigen_dptf.h 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/59632/1 diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index ea1efcf..f2ae769 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -70,6 +70,8 @@ return "TSR2"; case DPTF_TEMP_SENSOR_3: return "TSR3"; + case DPTF_TEMP_SENSOR_4: + return "TSR4"; case DPTF_TPCH: return "TPCH"; default: diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index c6ead0f..71a25b6 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -192,7 +192,7 @@ get_STA_value(config, DPTF_CHARGER), platform_info); - for (i = 0, participant = DPTF_TEMP_SENSOR_0; i < 4; ++i, ++participant) { + for (i = 0, participant = DPTF_TEMP_SENSOR_0; i < DPTF_MAX_TSR; ++i, ++participant) { snprintf(name, sizeof(name), "TSR%1d", i); dptf_write_generic_participant(name, DPTF_GENERIC_PARTICIPANT_TYPE_TSR, NULL, get_STA_value(config, participant), @@ -449,7 +449,7 @@ acpigen_pop_len(); /* Scope */ /* TSR options */ - for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) { + for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) { if (is_participant_used(config, p) && (config->options.tsr[i].hysteresis || config->options.tsr[i].desc)) { dptf_write_scope(p); diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index de57adc..758398d 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -24,6 +24,7 @@ DPTF_TEMP_SENSOR_1, DPTF_TEMP_SENSOR_2, DPTF_TEMP_SENSOR_3, + DPTF_TEMP_SENSOR_4, DPTF_TPCH, DPTF_PARTICIPANT_COUNT, }; @@ -44,7 +45,7 @@ DPTF_FIELD_UNUSED = 0xFFFFFFFFull, /* Max supported by DPTF */ - DPTF_MAX_TSR = 4, + DPTF_MAX_TSR = 5, }; /* Active Policy */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf9666bade23b9bb4f740c6c4df6ecf5227cfb45 Gerrit-Change-Number: 59632 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/*/include/data_fabric: make MMIO_NP definition SoC-specific
by Marshall Dawson (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59626 ) Change subject: soc/amd/*/include/data_fabric: make MMIO_NP definition SoC-specific ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64c06b84e2c0737b259077e7932f418306638e19 Gerrit-Change-Number: 59626 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 24 Nov 2021 16:20:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/data_fabric: use DF_ prefix for bit and shift defines
by Marshall Dawson (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59627 ) Change subject: soc/amd/*/data_fabric: use DF_ prefix for bit and shift defines ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a509ccc071aa51a67552fb9e7195358a76fe4dc Gerrit-Change-Number: 59627 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 24 Nov 2021 16:19:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/external: add skiboot (for QEMU/Power9)
by Sergii Dmytruk (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Martin Roth, Igor Bagnucki, Stefan Reinauer, Krystian Hebel, Timothy Pearson. Hello build bot (Jenkins), Martin Roth, Igor Bagnucki, Stefan Reinauer, Krystian Hebel, Timothy Pearson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58656 to look at the new patch set (#8). Change subject: payloads/external: add skiboot (for QEMU/Power9) ...................................................................... payloads/external: add skiboot (for QEMU/Power9) Add an option to build skiboot as a payload. This makes QEMU Power9 board simpler to use as skiboot is necessary anyway. Change-Id: I0b49ea7464c97cc2ff0d5030629deed549851372 Signed-off-by: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M Documentation/mainboard/emulation/qemu-power9.md M payloads/Makefile.inc M payloads/external/.gitignore M payloads/external/Makefile.inc A payloads/external/skiboot/Kconfig A payloads/external/skiboot/Kconfig.name A payloads/external/skiboot/Makefile M src/mainboard/emulation/qemu-power9/Kconfig 8 files changed, 105 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/58656/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/58656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b49ea7464c97cc2ff0d5030629deed549851372 Gerrit-Change-Number: 58656 Gerrit-PatchSet: 8 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/arch/ppc64/*: pass FDT address to payload
by Sergii Dmytruk (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Timothy Pearson, Ron Minnich. Hello build bot (Jenkins), Arthur Heymans, Timothy Pearson, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57084 to look at the new patch set (#18). Change subject: src/arch/ppc64/*: pass FDT address to payload ...................................................................... src/arch/ppc64/*: pass FDT address to payload It's available in %r3 in bootblock and needs to be passed first to romstage, then to ramstage, where it's put into CMBEM to be read on starting payload. Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/arch/ppc64/boot.c M src/arch/ppc64/bootblock_crt0.S M src/commonlib/include/commonlib/cbmem_id.h M src/mainboard/emulation/qemu-power9/memlayout.ld 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/57084/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/57084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Gerrit-Change-Number: 57084 Gerrit-PatchSet: 18 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/ppc64/boot.c: handle non-OPD entry point
by Sergii Dmytruk (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Timothy Pearson, Ron Minnich. Hello build bot (Jenkins), Arthur Heymans, Timothy Pearson, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57083 to look at the new patch set (#16). Change subject: arch/ppc64/boot.c: handle non-OPD entry point ...................................................................... arch/ppc64/boot.c: handle non-OPD entry point Change-Id: I309be370d66a808b355241fcee880883631f38ce Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/arch/ppc64/boot.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/57083/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/57083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I309be370d66a808b355241fcee880883631f38ce Gerrit-Change-Number: 57083 Gerrit-PatchSet: 16 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mainboard/emulation/qemu-power9: require hb-mode=on
by Sergii Dmytruk (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Paul Menzel, Timothy Pearson, Ron Minnich. Hello build bot (Jenkins), Arthur Heymans, Timothy Pearson, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57082 to look at the new patch set (#16). Change subject: src/mainboard/emulation/qemu-power9: require hb-mode=on ...................................................................... src/mainboard/emulation/qemu-power9: require hb-mode=on "hb-mode" is a -machine flag for QEMU. "hb" stands for Hostboot, which is OpenPower firmware created by IBM. QEMU for PPC64 can run initial program in two different modes: * hb-mode=off with load address 0x00000000 * hb-mode=on with load address 0x08000000 Real hardware always loads firmware at 0x08000000 and coreboot shouldn't require a special build to be run on QEMU. Memory layout is updated to reflect change of load address. Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/arch/ppc64/rom_media.c M src/arch/ppc64/stages.c M src/mainboard/emulation/qemu-power9/memlayout.ld 3 files changed, 33 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/57082/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/57082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054 Gerrit-Change-Number: 57082 Gerrit-PatchSet: 16 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021