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Hello build bot (Jenkins), Ron Minnich, Timothy Pearson,
I'd like you to reexamine a change. Please visit
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Change subject: src/mainboard/emulation/qemu-power9: add RAM detection
......................................................................
src/mainboard/emulation/qemu-power9: add RAM detection
Change-Id: Ie333294c7a311f6d47bdfbd1fc3cec0128cf63e7
Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev(a)3mdeb.com>
---
M src/mainboard/emulation/qemu-power9/cbmem.c
M src/mainboard/emulation/qemu-power9/mainboard.c
M src/mainboard/emulation/qemu-power9/memlayout.ld
M src/mainboard/emulation/qemu-power9/romstage.c
4 files changed, 13 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/57081/14
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Hello build bot (Jenkins), Arthur Heymans, Ron Minnich, Timothy Pearson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57079
to look at the new patch set (#14).
Change subject: src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard
......................................................................
src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard
Add initial implementation for booting on QEMU POWER9 emulation
Change-Id: I079c5b9ad564024dd13296ef75c263bdc40c9d39
Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev(a)3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
A Documentation/mainboard/emulation/qemu-power9.md
A configs/config.emulation_qemu_power9
A src/mainboard/emulation/qemu-power9/Kconfig
A src/mainboard/emulation/qemu-power9/Kconfig.name
A src/mainboard/emulation/qemu-power9/Makefile.inc
A src/mainboard/emulation/qemu-power9/board_info.txt
A src/mainboard/emulation/qemu-power9/cbmem.c
A src/mainboard/emulation/qemu-power9/devicetree.cb
A src/mainboard/emulation/qemu-power9/mainboard.c
A src/mainboard/emulation/qemu-power9/memlayout.ld
A src/mainboard/emulation/qemu-power9/romstage.c
11 files changed, 142 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/57079/14
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59630 )
Change subject: soc/amd/common/block/include/gpio_defs: rework de-glitching defines
......................................................................
soc/amd/common/block/include/gpio_defs: rework de-glitching defines
I found the name of the DEB_GLITCH_NONE definition a bit misleading, so
change it to DEB_GLITCH_REMOVE which should clarify what this will do.
The description for this value in the PPR/BKDG is "Remove glitch". This
also puts the define in line with GPIO_DEB_REMOVE_GLITCH which is the
only place where DEB_GLITCH_NONE/DEB_GLITCH_REMOVE is used.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I59648710e0ff28c2026e1b2cc7e433cafb2f2807
---
M src/soc/amd/common/block/include/amdblocks/gpio_defs.h
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/59630/1
diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h
index 0422079..1e3b172 100644
--- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h
+++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h
@@ -105,10 +105,10 @@
#define DEB_GLITCH_SHIFT 5
#define DEB_GLITCH_LOW 1
#define DEB_GLITCH_HIGH 2
-#define DEB_GLITCH_NONE 3
+#define DEB_GLITCH_REMOVE 3
#define GPIO_DEB_PRESERVE_LOW_GLITCH (DEB_GLITCH_LOW << DEB_GLITCH_SHIFT)
#define GPIO_DEB_PRESERVE_HIGH_GLITCH (DEB_GLITCH_HIGH << DEB_GLITCH_SHIFT)
-#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_NONE << DEB_GLITCH_SHIFT)
+#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_REMOVE << DEB_GLITCH_SHIFT)
#define GPIO_TIMEBASE_61uS 0
#define GPIO_TIMEBASE_183uS (1 << 4)
--
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57076 )
Change subject: ppc64/bootblock_crt0.S: minimal implementation for bootblock C environment
......................................................................
Patch Set 10:
(1 comment)
File src/arch/ppc64/bootblock_crt0.S:
https://review.coreboot.org/c/coreboot/+/57076/comment/4a3068e4_c58502f5
PS10, Line 64:
> are you working with 4spaces wide tabs or how comes that there are two tabs here (and in other cases […]
I suspect incorrect tab width was the reason. New patchset fixes it.
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Attention is currently required from: Krystian Hebel, Sergii Dmytruk, Timothy Pearson.
Hello build bot (Jenkins), Patrick Georgi, Arthur Heymans, Krystian Hebel, Timothy Pearson, Ron Minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57076
to look at the new patch set (#11).
Change subject: ppc64/bootblock_crt0.S: minimal implementation for bootblock C environment
......................................................................
ppc64/bootblock_crt0.S: minimal implementation for bootblock C environment
BSS is loaded as part of the bootblock, it is zeroed in the file so it
doesn't have to be cleared explicitly by the code.
Code for clearing is left as a comment along with a warning about alignment
requirements.
Vector operations are sometimes generated for code such as
'uint8_t x[32] = {0}', this results in an exception when vector registers
(VR) are not enabled. VSR (vector-scalar register) operations are also
enabled, there is no reason not to.
Change-Id: I878ef61619eb4a191805c8911d001312a0d717a0
Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
---
M src/arch/ppc64/Makefile.inc
D src/arch/ppc64/bootblock.S
A src/arch/ppc64/bootblock_crt0.S
3 files changed, 94 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/57076/11
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