coreboot-gerrit November 2021

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Change in coreboot[master]: soc/medaitek/mt8195: select MTK_DFD
by Rex-BC Chen (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59621 to look at the new patch set (#2). Change subject: soc/medaitek/mt8195: select MTK_DFD ...................................................................... soc/medaitek/mt8195: select MTK_DFD Select configuration MTK_DFD to enable DFD (design of debug), and we use it to identify reasons of reset issues. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ied711321efa592cf1bf7b318fe4d0aa155c15c70 --- M src/soc/mediatek/mt8195/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/59621/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied711321efa592cf1bf7b318fe4d0aa155c15c70 Gerrit-Change-Number: 59621 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Werner Zeh (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Nico Huber, Martin Roth, Mario Scheithauer, Lean Sheng Tan, Felix Held. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 56: (1 comment) File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/8404b7f2_a7a4079e PS52, Line 129: /* Set the ownership of these devices to PSE */ : params->PchPseDmaEnable[0] = PSE_Owned; : params->PchPseUartEnable[2] = PSE_Owned; : params->PchPseHsuartEnable[2] = PSE_Owned; : params->PchPseI2cEnable[2] = PSE_Owned; : params->PchPseTimedGpioEnable[0] = PSE_Owned; : params->PchPseTimedGpioEnable[1] = PSE_Owned; : /* Disable PSE DMA Sideband Interrupt for DMA 0 */ : params->PchPseDmaSbInterruptEnable[0] = 0; : /* Set the log output to PSE UART 2 */ : params->PchPseLogOutputChannel = 3; > Can you please mention the issue clearly in the commit message? I am nut sure if this should be placed in the commit message. Maybe it would be better to have it right here as a comment as it just is related to the ownership settings? -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 56 Gerrit-Owner: Lean Sheng Tan Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 24 Nov 2021 13:35:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/lynxpoint: Update `intel_me_status()` signature
by Angel Pons (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59625 ) Change subject: sb/intel/lynxpoint: Update `intel_me_status()` signature ...................................................................... sb/intel/lynxpoint: Update `intel_me_status()` signature Update the parameter types of `intel_me_status()` to not be pointers. Change-Id: I0fd577c49bec7a581c340fc2fcadcadd50b1a638 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/early_me.c M src/southbridge/intel/lynxpoint/me.c M src/southbridge/intel/lynxpoint/me.h M src/southbridge/intel/lynxpoint/me_status.c 4 files changed, 29 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/59625/1 diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index 9ab00cd..9f47740 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -25,7 +25,7 @@ union me_hfs hfs = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS) }; union me_hfs2 hfs2 = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS2) }; - intel_me_status(&hfs, &hfs2); + intel_me_status(hfs, hfs2); } int intel_early_me_init(void) diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c index 7ee7b2c..ca6aff7 100644 --- a/src/southbridge/intel/lynxpoint/me.c +++ b/src/southbridge/intel/lynxpoint/me.c @@ -581,7 +581,7 @@ union me_hfs2 hfs2 = { .raw = pci_read_config32(dev, PCI_ME_HFS2) }; /* Check and dump status */ - intel_me_status(&hfs, &hfs2); + intel_me_status(hfs, hfs2); /* Check Current Working State */ switch (hfs.working_state) { diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index 45649e0e..fe8b026 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -334,7 +334,7 @@ }; /* Defined in me_status.c for both romstage and ramstage */ -void intel_me_status(union me_hfs *hfs, union me_hfs2 *hfs2); +void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2); void intel_early_me_status(void); int intel_early_me_init(void); diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 3f4d9bc..f9e0fcb 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -123,72 +123,72 @@ [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match", }; -void intel_me_status(union me_hfs *hfs, union me_hfs2 *hfs2) +void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2) { if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) return; /* Check Current States */ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", - hfs->fpt_bad ? "BAD" : "OK"); + hfs.fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", - hfs->ft_bup_ld_flr ? "YES" : "NO"); + hfs.ft_bup_ld_flr ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", - hfs->fw_init_complete ? "YES" : "NO"); + hfs.fw_init_complete ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfs->mfg_mode ? "YES" : "NO"); + hfs.mfg_mode ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", - hfs->boot_options_present ? "YES" : "NO"); + hfs.boot_options_present ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", - hfs->update_in_progress ? "YES" : "NO"); + hfs.update_in_progress ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Current Working State : %s\n", - me_cws_values[hfs->working_state]); + me_cws_values[hfs.working_state]); printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", - me_opstate_values[hfs->operation_state]); + me_opstate_values[hfs.operation_state]); printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", - me_opmode_values[hfs->operation_mode]); + me_opmode_values[hfs.operation_mode]); printk(BIOS_DEBUG, "ME: Error Code : %s\n", - me_error_values[hfs->error_code]); + me_error_values[hfs.error_code]); printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", - me_progress_values[hfs2->progress_code]); + me_progress_values[hfs2.progress_code]); printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", - me_pmevent_values[hfs2->current_pmevent]); + me_pmevent_values[hfs2.current_pmevent]); printk(BIOS_DEBUG, "ME: Progress Phase State : "); - switch (hfs2->progress_code) { + switch (hfs2.progress_code) { case ME_HFS2_PHASE_ROM: /* ROM Phase */ printk(BIOS_DEBUG, "%s", - me_progress_rom_values[hfs2->current_state]); + me_progress_rom_values[hfs2.current_state]); break; case ME_HFS2_PHASE_BUP: /* Bringup Phase */ - if (hfs2->current_state < ARRAY_SIZE(me_progress_bup_values) - && me_progress_bup_values[hfs2->current_state]) + if (hfs2.current_state < ARRAY_SIZE(me_progress_bup_values) + && me_progress_bup_values[hfs2.current_state]) printk(BIOS_DEBUG, "%s", - me_progress_bup_values[hfs2->current_state]); + me_progress_bup_values[hfs2.current_state]); else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + printk(BIOS_DEBUG, "0x%02x", hfs2.current_state); break; case ME_HFS2_PHASE_POLICY: /* Policy Module Phase */ - if (hfs2->current_state < ARRAY_SIZE(me_progress_policy_values) - && me_progress_policy_values[hfs2->current_state]) + if (hfs2.current_state < ARRAY_SIZE(me_progress_policy_values) + && me_progress_policy_values[hfs2.current_state]) printk(BIOS_DEBUG, "%s", - me_progress_policy_values[hfs2->current_state]); + me_progress_policy_values[hfs2.current_state]); else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + printk(BIOS_DEBUG, "0x%02x", hfs2.current_state); break; case ME_HFS2_PHASE_HOST_COMM: /* Host Communication Phase */ - if (!hfs2->current_state) + if (!hfs2.current_state) printk(BIOS_DEBUG, "Host communication established"); else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + printk(BIOS_DEBUG, "0x%02x", hfs2.current_state); break; default: printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x", - hfs2->progress_code, hfs2->current_state); + hfs2.progress_code, hfs2.current_state); } printk(BIOS_DEBUG, "\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/59625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd577c49bec7a581c340fc2fcadcadd50b1a638 Gerrit-Change-Number: 59625 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint/me.c: Refactor MEI CSR functions
by Angel Pons (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59624 ) Change subject: sb/intel/lynxpoint/me.c: Refactor MEI CSR functions ...................................................................... sb/intel/lynxpoint/me.c: Refactor MEI CSR functions Change the signature of MEI CSR functions to reduce pointer usage. Change-Id: I1e4885daf8b3e11056421e663e67c8f360699a98 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/me.c 1 file changed, 31 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/59624/1 diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c index 15e2db0..7ee7b2c 100644 --- a/src/southbridge/intel/lynxpoint/me.c +++ b/src/southbridge/intel/lynxpoint/me.c @@ -73,22 +73,24 @@ * ME/MEI access helpers using memcpy to avoid aliasing. */ -static inline void read_host_csr(union mei_csr *csr) +static inline union mei_csr read_host_csr(void) { - csr->raw = read32(mei_base_address + MEI_H_CSR); - mei_dump(csr->raw, MEI_H_CSR, "READ"); + union mei_csr csr = { .raw = read32(mei_base_address + MEI_H_CSR) }; + mei_dump(csr.raw, MEI_H_CSR, "READ"); + return csr; } -static inline void write_host_csr(union mei_csr *csr) +static inline void write_host_csr(union mei_csr csr) { - write32(mei_base_address + MEI_H_CSR, csr->raw); - mei_dump(csr->raw, MEI_H_CSR, "WRITE"); + write32(mei_base_address + MEI_H_CSR, csr.raw); + mei_dump(csr.raw, MEI_H_CSR, "WRITE"); } -static inline void read_me_csr(union mei_csr *csr) +static inline union mei_csr read_me_csr(void) { - csr->raw = read32(mei_base_address + MEI_ME_CSR_HA); - mei_dump(csr->raw, MEI_ME_CSR_HA, "READ"); + union mei_csr csr = { .raw = read32(mei_base_address + MEI_ME_CSR_HA) }; + mei_dump(csr.raw, MEI_ME_CSR_HA, "READ"); + return csr; } static inline void write_cb(u32 dword) @@ -111,7 +113,7 @@ unsigned int try = ME_RETRY; while (try--) { - read_me_csr(&me); + me = read_me_csr(); if (me.ready) return 0; udelay(ME_DELAY); @@ -129,20 +131,20 @@ return; /* Reset host and ME circular buffers for next message */ - read_host_csr(&host); + host = read_host_csr(); host.reset = 1; host.interrupt_generate = 1; - write_host_csr(&host); + write_host_csr(host); if (mei_wait_for_me_ready() < 0) return; /* Re-init and indicate host is ready */ - read_host_csr(&host); + host = read_host_csr(); host.interrupt_generate = 1; host.ready = 1; host.reset = 0; - write_host_csr(&host); + write_host_csr(host); } static int mei_send_packet(union mei_header *mei, void *req_data) @@ -167,11 +169,11 @@ * Make sure there is still room left in the circular buffer. * Reset the buffer pointers if the requested message will not fit. */ - read_host_csr(&host); + host = read_host_csr(); if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); mei_reset(); - read_host_csr(&host); + host = read_host_csr(); } /* Ensure the requested length will fit in the circular buffer. */ @@ -191,9 +193,9 @@ write_cb(*data++); /* Generate interrupt to the ME */ - read_host_csr(&host); + host = read_host_csr(); host.interrupt_generate = 1; - write_host_csr(&host); + write_host_csr(host); /* Make sure ME is ready after sending request data */ return mei_wait_for_me_ready(); @@ -214,7 +216,7 @@ int remain = req_bytes - current; int buf_len; - read_host_csr(&host); + host = read_host_csr(); buf_len = host.buffer_depth - host.buffer_write_ptr; if (buf_len > remain) { @@ -270,7 +272,7 @@ * expected number of dwords are present in the circular buffer. */ for (n = ME_RETRY; n; --n) { - read_me_csr(&me); + me = read_me_csr(); if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) break; udelay(ME_DELAY); @@ -318,10 +320,10 @@ *data++ = read_cb(); /* Tell the ME that we have consumed the response */ - read_host_csr(&host); + host = read_host_csr(); host.interrupt_status = 1; host.interrupt_generate = 1; - write_host_csr(&host); + write_host_csr(host); return mei_wait_for_me_ready(); } @@ -398,10 +400,10 @@ pci_write_config32(dev, PCI_ME_H_GS2, PCI_ME_MBP_GIVE_UP); - read_host_csr(&csr); + csr = read_host_csr(); csr.reset = 1; csr.interrupt_generate = 1; - write_host_csr(&csr); + write_host_csr(csr); } /* @@ -654,11 +656,11 @@ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Clean up status for next message */ - read_host_csr(&host); + host = read_host_csr(); host.interrupt_generate = 1; host.ready = 1; host.reset = 0; - write_host_csr(&host); + write_host_csr(host); return 0; } @@ -710,8 +712,7 @@ static u32 me_to_host_words_pending(void) { - union mei_csr me; - read_me_csr(&me); + union mei_csr me = read_me_csr(); if (!me.ready) return 0; return (me.buffer_write_ptr - me.buffer_read_ptr) & @@ -774,9 +775,9 @@ } /* Signal to the ME that the host has finished reading the MBP. */ - read_host_csr(&host); + host = read_host_csr(); host.interrupt_generate = 1; - write_host_csr(&host); + write_host_csr(host); /* Dump out the MBP contents. */ if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { -- To view, visit https://review.coreboot.org/c/coreboot/+/59624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e4885daf8b3e11056421e663e67c8f360699a98 Gerrit-Change-Number: 59624 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Use unions for MEI registers
by Angel Pons (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59623 ) Change subject: sb/intel/lynxpoint: Use unions for MEI registers ...................................................................... sb/intel/lynxpoint: Use unions for MEI registers Wrap bitfield structs in unions to reduce pointer usage. This adds more uses of the `mei_dump()` function, only used for debugging. Refactoring the MEI CSR functions to not use pointers is done in a follow-up. Change-Id: I4defbb8c0e7812bf95c672ce529959f67c34537a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/me.c M src/southbridge/intel/lynxpoint/me.h 2 files changed, 69 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/59623/1 diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c index a1625e8..15e2db0 100644 --- a/src/southbridge/intel/lynxpoint/me.c +++ b/src/southbridge/intel/lynxpoint/me.c @@ -40,9 +40,9 @@ /* MMIO base address for MEI interface */ static u8 *mei_base_address; -static void mei_dump(void *ptr, int dword, int offset, const char *type) +static void mei_dump(u32 dword, int offset, const char *type) { - struct mei_csr *csr; + union mei_csr csr; if (!CONFIG(DEBUG_INTEL_ME)) return; @@ -52,16 +52,12 @@ switch (offset) { case MEI_H_CSR: case MEI_ME_CSR_HA: - csr = ptr; - if (!csr) { - printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); - break; - } + csr.raw = dword; printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " - "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, - csr->buffer_read_ptr, csr->buffer_write_ptr, - csr->ready, csr->reset, csr->interrupt_generate, - csr->interrupt_status, csr->interrupt_enable); + "reset=%u ig=%u is=%u ie=%u\n", csr.buffer_depth, + csr.buffer_read_ptr, csr.buffer_write_ptr, + csr.ready, csr.reset, csr.interrupt_generate, + csr.interrupt_status, csr.interrupt_enable); break; case MEI_ME_CB_RW: case MEI_H_CB_WW: @@ -77,53 +73,41 @@ * ME/MEI access helpers using memcpy to avoid aliasing. */ -static inline void mei_read_dword_ptr(void *ptr, int offset) +static inline void read_host_csr(union mei_csr *csr) { - u32 dword = read32(mei_base_address + offset); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "READ"); + csr->raw = read32(mei_base_address + MEI_H_CSR); + mei_dump(csr->raw, MEI_H_CSR, "READ"); } -static inline void mei_write_dword_ptr(void *ptr, int offset) +static inline void write_host_csr(union mei_csr *csr) { - u32 dword = 0; - memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + offset, dword); - mei_dump(ptr, dword, offset, "WRITE"); + write32(mei_base_address + MEI_H_CSR, csr->raw); + mei_dump(csr->raw, MEI_H_CSR, "WRITE"); } -static inline void read_host_csr(struct mei_csr *csr) +static inline void read_me_csr(union mei_csr *csr) { - mei_read_dword_ptr(csr, MEI_H_CSR); -} - -static inline void write_host_csr(struct mei_csr *csr) -{ - mei_write_dword_ptr(csr, MEI_H_CSR); -} - -static inline void read_me_csr(struct mei_csr *csr) -{ - mei_read_dword_ptr(csr, MEI_ME_CSR_HA); + csr->raw = read32(mei_base_address + MEI_ME_CSR_HA); + mei_dump(csr->raw, MEI_ME_CSR_HA, "READ"); } static inline void write_cb(u32 dword) { write32(mei_base_address + MEI_H_CB_WW, dword); - mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); + mei_dump(dword, MEI_H_CB_WW, "WRITE"); } static inline u32 read_cb(void) { u32 dword = read32(mei_base_address + MEI_ME_CB_RW); - mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); + mei_dump(dword, MEI_ME_CB_RW, "READ"); return dword; } /* Wait for ME ready bit to be asserted */ static int mei_wait_for_me_ready(void) { - struct mei_csr me; + union mei_csr me; unsigned int try = ME_RETRY; while (try--) { @@ -139,7 +123,7 @@ static void mei_reset(void) { - struct mei_csr host; + union mei_csr host; if (mei_wait_for_me_ready() < 0) return; @@ -161,9 +145,9 @@ write_host_csr(&host); } -static int mei_send_packet(struct mei_header *mei, void *req_data) +static int mei_send_packet(union mei_header *mei, void *req_data) { - struct mei_csr host; + union mei_csr host; unsigned int ndata, n; u32 *data; @@ -198,7 +182,7 @@ } /* Write MEI header */ - mei_write_dword_ptr(mei, MEI_H_CB_WW); + write_cb(mei->raw); ndata--; /* Write message data */ @@ -218,11 +202,11 @@ static int mei_send_data(u8 me_address, u8 host_address, void *req_data, int req_bytes) { - struct mei_header header = { + union mei_header header = { .client_address = me_address, .host_address = host_address, }; - struct mei_csr host; + union mei_csr host; int current = 0; u8 *req_ptr = req_data; @@ -254,7 +238,7 @@ static int mei_send_header(u8 me_address, u8 host_address, void *header, int header_len, int complete) { - struct mei_header mei = { + union mei_header mei = { .client_address = me_address, .host_address = host_address, .length = header_len, @@ -266,8 +250,8 @@ static int mei_recv_msg(void *header, int header_bytes, void *rsp_data, int rsp_bytes) { - struct mei_header mei_rsp; - struct mei_csr me, host; + union mei_header mei_rsp; + union mei_csr me, host; unsigned int ndata, n; unsigned int expected; u32 *data; @@ -299,7 +283,7 @@ } /* Read and verify MEI response header from the ME */ - mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); + mei_rsp.raw = read_cb(); if (!mei_rsp.is_complete) { printk(BIOS_ERR, "ME: response is not complete\n"); return -1; @@ -410,7 +394,7 @@ */ static void intel_me_mbp_give_up(struct device *dev) { - struct mei_csr csr; + union mei_csr csr; pci_write_config32(dev, PCI_ME_H_GS2, PCI_ME_MBP_GIVE_UP); @@ -656,7 +640,7 @@ static int intel_mei_setup(struct device *dev) { struct resource *res; - struct mei_csr host; + union mei_csr host; /* Find the MMIO base for the ME interface */ res = probe_resource(dev, PCI_BASE_ADDRESS_0); @@ -726,7 +710,7 @@ static u32 me_to_host_words_pending(void) { - struct mei_csr me; + union mei_csr me; read_me_csr(&me); if (!me.ready) return 0; @@ -735,7 +719,7 @@ } struct mbp_payload { - struct mbp_header header; + union mbp_header header; u32 data[0]; }; @@ -747,9 +731,9 @@ */ static int intel_me_read_mbp(struct me_bios_payload *mbp_data, struct device *dev) { - struct mbp_header mbp_hdr; + union mbp_header mbp_hdr; u32 me2host_pending; - struct mei_csr host; + union mei_csr host; union me_hfs2 hfs2 = { .raw = pci_read_config32(dev, PCI_ME_HFS2) }; struct mbp_payload *mbp; int i; @@ -766,7 +750,7 @@ } /* we know for sure that at least the header is there */ - mei_read_dword_ptr(&mbp_hdr, MEI_ME_CB_RW); + mbp_hdr.raw = read_cb(); if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) || (me2host_pending < mbp_hdr.mbp_size)) { @@ -785,7 +769,7 @@ i = 0; while (i != me2host_pending) { - mei_read_dword_ptr(&mbp->data[i], MEI_ME_CB_RW); + mbp->data[i] = read_cb(); i++; } diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index 6b072f9..45649e0e 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -221,17 +221,20 @@ #define MEI_ME_CB_RW 0x08 #define MEI_ME_CSR_HA 0x0c -struct mei_csr { - u32 interrupt_enable: 1; - u32 interrupt_status: 1; - u32 interrupt_generate: 1; - u32 ready: 1; - u32 reset: 1; - u32 reserved: 3; - u32 buffer_read_ptr: 8; - u32 buffer_write_ptr: 8; - u32 buffer_depth: 8; -} __packed; +union mei_csr { + struct __packed { + u32 interrupt_enable: 1; + u32 interrupt_status: 1; + u32 interrupt_generate: 1; + u32 ready: 1; + u32 reset: 1; + u32 reserved: 3; + u32 buffer_read_ptr: 8; + u32 buffer_write_ptr: 8; + u32 buffer_depth: 8; + }; + u32 raw; +}; #define MEI_ADDRESS_CORE 0x01 #define MEI_ADDRESS_AMT 0x02 @@ -243,13 +246,16 @@ #define MEI_HOST_ADDRESS 0 -struct mei_header { - u32 client_address: 8; - u32 host_address: 8; - u32 length: 9; - u32 reserved: 6; - u32 is_complete: 1; -} __packed; +union mei_header { + struct __packed { + u32 client_address: 8; + u32 host_address: 8; + u32 length: 9; + u32 reserved: 6; + u32 is_complete: 1; + }; + u32 raw; +}; #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GROUP_ID_FWCAPS 0x03 @@ -368,11 +374,14 @@ #define MBP_IDENT(appid, item) \ MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) -struct mbp_header { - u32 mbp_size : 8; - u32 num_entries : 8; - u32 rsvd : 16; -} __packed; +union mbp_header { + struct __packed { + u32 mbp_size : 8; + u32 num_entries : 8; + u32 rsvd : 16; + }; + u32 raw; +}; struct mbp_item_header { u32 app_id : 8; -- To view, visit https://review.coreboot.org/c/coreboot/+/59623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4defbb8c0e7812bf95c672ce529959f67c34537a Gerrit-Change-Number: 59623 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: sb/intel/lynxpoint: Use unions for ME PCI registers
by Angel Pons (Code Review) 24 Nov '21

24 Nov '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59622 ) Change subject: sb/intel/lynxpoint: Use unions for ME PCI registers ...................................................................... sb/intel/lynxpoint: Use unions for ME PCI registers Wrap bitfield structs in unions to reduce pointer usage. Change-Id: I8ac901211beb0ef24dff926b1a06004a99e68bda Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/early_me.c M src/southbridge/intel/lynxpoint/me.c M src/southbridge/intel/lynxpoint/me.h M src/southbridge/intel/lynxpoint/me_status.c 4 files changed, 87 insertions(+), 103 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/59622/1 diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index e5ce3f5..9ab00cd 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -20,26 +20,10 @@ [ME_HFS_ACK_CONTINUE] = "Continue to boot" }; -static inline void pci_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = pci_read_config32(PCH_ME_DEV, offset); - memcpy(ptr, &dword, sizeof(dword)); -} - -static inline void pci_write_dword_ptr(void *ptr, int offset) -{ - u32 dword = 0; - memcpy(&dword, ptr, sizeof(dword)); - pci_write_config32(PCH_ME_DEV, offset, dword); -} - void intel_early_me_status(void) { - struct me_hfs hfs; - struct me_hfs2 hfs2; - - pci_read_dword_ptr(&hfs, PCI_ME_HFS); - pci_read_dword_ptr(&hfs2, PCI_ME_HFS2); + union me_hfs hfs = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS) }; + union me_hfs2 hfs2 = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS2) }; intel_me_status(&hfs, &hfs2); } @@ -47,15 +31,15 @@ int intel_early_me_init(void) { int count; - struct me_uma uma; - struct me_hfs hfs; + union me_uma uma; + union me_hfs hfs; printk(BIOS_INFO, "Intel ME early init\n"); /* Wait for ME UMA SIZE VALID bit to be set */ /* FIXME: ME9 BGW indicates a 5 sec poll timeout. */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&uma, PCI_ME_UMA); + uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA); if (uma.valid) break; udelay(ME_DELAY); @@ -66,7 +50,7 @@ } /* Check for valid firmware */ - pci_read_dword_ptr(&hfs, PCI_ME_HFS); + hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); if (hfs.fpt_bad) { printk(BIOS_WARNING, "WARNING: ME has bad firmware\n"); return -1; @@ -78,9 +62,8 @@ int intel_early_me_uma_size(void) { - struct me_uma uma; + union me_uma uma = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA) }; - pci_read_dword_ptr(&uma, PCI_ME_UMA); if (uma.valid) { printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size); return uma.size; @@ -108,8 +91,8 @@ u8 reset; int count; u32 mebase_l, mebase_h; - struct me_hfs hfs; - struct me_did did = { + union me_hfs hfs; + union me_did did = { .init_done = ME_INIT_DONE, .status = status }; @@ -123,7 +106,7 @@ printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, " "UMA base: 0x%04x\n", status, did.uma_base); - pci_write_dword_ptr(&did, PCI_ME_H_GS); + pci_write_config32(PCH_ME_DEV, PCI_ME_H_GS, did.raw); /* * The ME firmware does not respond with an ACK when NOMEM or ERROR @@ -134,7 +117,7 @@ /* Must wait for ME acknowledgement */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&hfs, PCI_ME_HFS); + hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); if (hfs.bios_msg_ack) break; udelay(ME_DELAY); diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c index 9196fb3..a1625e8 100644 --- a/src/southbridge/intel/lynxpoint/me.c +++ b/src/southbridge/intel/lynxpoint/me.c @@ -92,13 +92,6 @@ mei_dump(ptr, dword, offset, "WRITE"); } -static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) -{ - u32 dword = pci_read_config32(dev, offset); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "PCI READ"); -} - static inline void read_host_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_H_CSR); @@ -434,11 +427,11 @@ static void intel_me_mbp_clear(struct device *dev) { int count; - struct me_hfs2 hfs2; + union me_hfs2 hfs2; /* Wait for the mbp_cleared indicator */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); + hfs2.raw = pci_read_config32(dev, PCI_ME_HFS2); if (hfs2.mbp_cleared) break; udelay(ME_DELAY); @@ -539,7 +532,7 @@ void intel_me_finalize(struct device *dev) { - struct me_hfs hfs; + union me_hfs hfs; u32 reg32; reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -553,8 +546,7 @@ intel_me_mbp_clear(dev); /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(dev, PCI_ME_HFS); - memcpy(&hfs, &reg32, sizeof(u32)); + hfs.raw = pci_read_config32(dev, PCI_ME_HFS); /* Abort and leave device alone if not normal mode */ if (hfs.fpt_bad || @@ -599,11 +591,8 @@ static enum me_bios_path intel_me_path(struct device *dev) { enum me_bios_path path = ME_DISABLE_BIOS_PATH; - struct me_hfs hfs; - struct me_hfs2 hfs2; - - pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); - pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); + union me_hfs hfs = { .raw = pci_read_config32(dev, PCI_ME_HFS) }; + union me_hfs2 hfs2 = { .raw = pci_read_config32(dev, PCI_ME_HFS2) }; /* Check and dump status */ intel_me_status(&hfs, &hfs2); @@ -693,11 +682,10 @@ /* Read the Extend register hash of ME firmware */ static int intel_me_extend_valid(struct device *dev) { - struct me_heres status; + union me_heres status = { .raw = pci_read_config32(dev, PCI_ME_HERES) }; u32 extend[8] = {0}; int i, count = 0; - pci_read_dword_ptr(dev, &status, PCI_ME_HERES); if (!status.extend_feature_present) { printk(BIOS_ERR, "ME: Extend Feature not present\n"); return -1; @@ -762,12 +750,10 @@ struct mbp_header mbp_hdr; u32 me2host_pending; struct mei_csr host; - struct me_hfs2 hfs2; + union me_hfs2 hfs2 = { .raw = pci_read_config32(dev, PCI_ME_HFS2) }; struct mbp_payload *mbp; int i; - pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); - if (!hfs2.mbp_rdy) { printk(BIOS_ERR, "ME: MBP not ready\n"); goto mbp_failure; diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index cf797f3..6b072f9 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -50,31 +50,37 @@ #define ME_HFS_ACK_GBL_RESET 6 #define ME_HFS_ACK_CONTINUE 7 -struct me_hfs { - u32 working_state: 4; - u32 mfg_mode: 1; - u32 fpt_bad: 1; - u32 operation_state: 3; - u32 fw_init_complete: 1; - u32 ft_bup_ld_flr: 1; - u32 update_in_progress: 1; - u32 error_code: 4; - u32 operation_mode: 4; - u32 reserved: 4; - u32 boot_options_present: 1; - u32 ack_data: 3; - u32 bios_msg_ack: 4; -} __packed; +union me_hfs { + struct __packed { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reserved: 4; + u32 boot_options_present: 1; + u32 ack_data: 3; + u32 bios_msg_ack: 4; + }; + u32 raw; +}; #define PCI_ME_UMA 0x44 -struct me_uma { - u32 size: 6; - u32 reserved_1: 10; - u32 valid: 1; - u32 reserved_0: 14; - u32 set_to_one: 1; -} __packed; +union me_uma { + struct __packed { + u32 size: 6; + u32 reserved_1: 10; + u32 valid: 1; + u32 reserved_0: 14; + u32 set_to_one: 1; + }; + u32 raw; +}; #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -83,13 +89,16 @@ #define ME_INIT_STATUS_ERROR 2 #define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */ -struct me_did { - u32 uma_base: 16; - u32 reserved: 7; - u32 rapid_start: 1; - u32 status: 4; - u32 init_done: 4; -} __packed; +union me_did { + struct __packed { + u32 uma_base: 16; + u32 reserved: 7; + u32 rapid_start: 1; + u32 status: 4; + u32 init_done: 4; + }; + u32 raw; +}; /* * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according @@ -165,22 +174,25 @@ #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb #define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc -struct me_hfs2 { - u32 bist_in_progress: 1; - u32 reserved1: 2; - u32 invoke_mebx: 1; - u32 cpu_replaced_sts: 1; - u32 mbp_rdy: 1; - u32 mfs_failure: 1; - u32 warm_reset_request: 1; - u32 cpu_replaced_valid: 1; - u32 reserved2: 4; - u32 mbp_cleared: 1; - u32 reserved3: 2; - u32 current_state: 8; - u32 current_pmevent: 4; - u32 progress_code: 4; -} __packed; +union me_hfs2 { + struct __packed { + u32 bist_in_progress: 1; + u32 reserved1: 2; + u32 invoke_mebx: 1; + u32 cpu_replaced_sts: 1; + u32 mbp_rdy: 1; + u32 mfs_failure: 1; + u32 warm_reset_request: 1; + u32 cpu_replaced_valid: 1; + u32 reserved2: 4; + u32 mbp_cleared: 1; + u32 reserved3: 2; + u32 current_state: 8; + u32 current_pmevent: 4; + u32 progress_code: 4; + }; + u32 raw; +}; #define PCI_ME_H_GS2 0x70 #define PCI_ME_MBP_GIVE_UP 0x01 @@ -190,12 +202,15 @@ #define PCI_ME_EXT_SHA256 0x02 #define PCI_ME_HER(x) (0xc0+(4*(x))) -struct me_heres { - u32 extend_reg_algorithm: 4; - u32 reserved: 26; - u32 extend_feature_present: 1; - u32 extend_reg_valid: 1; -} __packed; +union me_heres { + struct __packed { + u32 extend_reg_algorithm: 4; + u32 reserved: 26; + u32 extend_feature_present: 1; + u32 extend_reg_valid: 1; + }; + u32 raw; +}; /* * Management Engine MEI registers @@ -313,7 +328,7 @@ }; /* Defined in me_status.c for both romstage and ramstage */ -void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2); +void intel_me_status(union me_hfs *hfs, union me_hfs2 *hfs2); void intel_early_me_status(void); int intel_early_me_init(void); diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index fb4490f..3f4d9bc 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -123,7 +123,7 @@ [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match", }; -void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2) +void intel_me_status(union me_hfs *hfs, union me_hfs2 *hfs2) { if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/59622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ac901211beb0ef24dff926b1a06004a99e68bda Gerrit-Change-Number: 59622 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: drivers/analogix/anx7625: Fix return code handling
by Felix Held (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Paul Menzel, Yu-Ping Wu. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59539 ) Change subject: drivers/analogix/anx7625: Fix return code handling ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > i'd say that a function that returns a signed integer as status code is supposed to return a negativ […] using enum cb_err as return value type of platform_i2c_transfer might be even better -- To view, visit https://review.coreboot.org/c/coreboot/+/59539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955b9aae11e20d75fac414d15714330e364dad2f Gerrit-Change-Number: 59539 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Wei-Shun Chang <weishunc(a)google.com> Gerrit-Reviewer: Xin Ji <xji(a)analogix.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 24 Nov 2021 13:08:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/analogix/anx7625: Fix return code handling
by Felix Held (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Paul Menzel, Yu-Ping Wu. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59539 ) Change subject: drivers/analogix/anx7625: Fix return code handling ...................................................................... Patch Set 2: Code-Review-1 (1 comment) Patchset: PS2: i'd say that a function that returns a signed integer as status code is supposed to return a negative value in all failure cases. so the proper fix would be to make platform_i2c_transfer return a negative value in those failure cases, so that the same bug can't happen in other drivers -- To view, visit https://review.coreboot.org/c/coreboot/+/59539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955b9aae11e20d75fac414d15714330e364dad2f Gerrit-Change-Number: 59539 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Wei-Shun Chang <weishunc(a)google.com> Gerrit-Reviewer: Xin Ji <xji(a)analogix.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 24 Nov 2021 13:06:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/medaitek/mt8195: select MTK_DFD
by Rex-BC Chen (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59621 ) Change subject: soc/medaitek/mt8195: select MTK_DFD ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied711321efa592cf1bf7b318fe4d0aa155c15c70 Gerrit-Change-Number: 59621 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 24 Nov 2021 13:02:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/medaitek/mt8195: select MTK_DFD
by Rex-BC Chen (Code Review) 24 Nov '21

24 Nov '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59621 ) Change subject: soc/medaitek/mt8195: select MTK_DFD ...................................................................... soc/medaitek/mt8195: select MTK_DFD Select configuration MTK_DFD to enable design of debug feature for Tomato debug purpose. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ied711321efa592cf1bf7b318fe4d0aa155c15c70 --- M src/soc/mediatek/mt8195/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/59621/1 diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig index d1cb09b..0c9853d 100644 --- a/src/soc/mediatek/mt8195/Kconfig +++ b/src/soc/mediatek/mt8195/Kconfig @@ -10,6 +10,7 @@ select HAVE_UART_SPECIAL select SOC_MEDIATEK_COMMON select DPM_FOUR_CHANNEL + select MTK_DFD if SOC_MEDIATEK_MT8195 -- To view, visit https://review.coreboot.org/c/coreboot/+/59621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied711321efa592cf1bf7b318fe4d0aa155c15c70 Gerrit-Change-Number: 59621 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021