Patrick Georgi has restored this change. ( https://review.coreboot.org/c/coreboot/+/57527 )
Change subject: util/testing: Give meaningful error if intel-sec-tools aren't around
......................................................................
Restored
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59616 )
Change subject: commonlib/cbmem_id.h: Fix typo in macro name
......................................................................
Patch Set 1: Code-Review+2
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57076 )
Change subject: ppc64/bootblock_crt0.S: minimal implementation for bootblock C environment
......................................................................
Patch Set 10: Code-Review+2
(2 comments)
Patchset:
PS10:
with coding style weirdness resolved: LGTM
File src/arch/ppc64/bootblock_crt0.S:
https://review.coreboot.org/c/coreboot/+/57076/comment/b7c99c7e_6d39aab3
PS10, Line 64:
are you working with 4spaces wide tabs or how comes that there are two tabs here (and in other cases where the opcode has 2 or 3 letters)?
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59496 )
Change subject: libpayload/tests: Fix mocks __real_<func> symbol creation
......................................................................
libpayload/tests: Fix mocks __real_<func> symbol creation
There were escape backslashes around regular expression passed to grep.
Because of that, grep was returning empty results as a consequence of
pattern mismatch, and thus symbols pointing to original functions were
not created correctly.
Change-Id: I751109735b6c56824df9a560ae989bf062a0e9a6
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59496
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
M payloads/libpayload/tests/Makefile.inc
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Julius Werner: Looks good to me, approved
diff --git a/payloads/libpayload/tests/Makefile.inc b/payloads/libpayload/tests/Makefile.inc
index e4babb1..ba465b0 100644
--- a/payloads/libpayload/tests/Makefile.inc
+++ b/payloads/libpayload/tests/Makefile.inc
@@ -140,7 +140,7 @@
objcopy_wrap_flags=''; \
for sym in $$($(1)-mocks); do \
sym_line="$$$$($(HOSTOBJDUMP) -t $$@.orig \
- | grep -E \"[0-9a-fA-F]+\\s+w\\s+F\\s+.*\\s$$$$sym$$$$\")"; \
+ | grep -E "[0-9a-fA-F]+\\s+w\\s+F\\s+.*\\s+$$$$sym$$$$")"; \
if [ ! -z "$$$$sym_line" ] ; then \
addr="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$1 }')"; \
section="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$(NF - 2) }')"; \
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
......................................................................
soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
The patch implements ACPI CPPCv3 package. It implements and updates the
following methods:
generate_cppc_entries(): Updates method to support CPPCv3 package
acpigen_write_CPPC_hybrid_method(): It generates ACPI code to implement
_CPC method and calls XPPPC method.
acpi_write_xppc_method(): It generates ACPI code if cpu supports
Nominal Frequency. It generates ACPI code which sets Nominal Frequency
and updates Nominal Performance. It uses below calculation to update
the Nominal Frequency and Nominal Performance:
Nominal Frequency = Max non-turbo ratio * cpu_bus_frequency
Nominal Performance = Max non-turn ratio * cpu scaling factor
CPU scaling factor varies in the hybrid core environment. So, the
generated ACPI code updates Nominal Performance based on the CPU's
scaling factor.
TEST=Verified CPPCv3 package and XPP3 method are getting created in the
SSDT table.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Signed-off-by: ravindr1 <ravindra(a)intel.com>
Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca
---
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/acpi/cpu_hybrid.c
M src/soc/intel/common/block/include/intelblocks/acpi.h
3 files changed, 131 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/59359/3
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Change subject: soc/intel/alderlake, soc/common: Add method to determine the cpu type mask
......................................................................
soc/intel/alderlake, soc/common: Add method to determine the cpu type mask
get_cpu_type_bitmask(): It returns the cpu type mask.
set_cpu_type_bitmask(): It determines the cpu type (big or small) that
is executing the function, and marks the bit location which is
corresponds to the executing cpu's index if the cpu type is big.
get_cpu_index(): It determines the index from LAPIC Ids. This is
required to expose CPPC3 package in ascending order of CPUs' LAPIC ids.
So, the function returns CPU's position from ascending order list of
LAPIC ids.
get_cpu_type(): It returns the type of CPU that executing the function.
Also, it calls the set_cpu_type_bitmask() from soc/alderlake/cpu.c
TEST=Tested CPU index calculation, core type determination on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b
---
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/acpi/Makefile.inc
A src/soc/intel/common/block/acpi/cpu_hybrid.c
M src/soc/intel/common/block/include/intelblocks/acpi.h
5 files changed, 91 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/59360/3
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Change subject: soc/intel/common: Add CPU related APIs
......................................................................
soc/intel/common: Add CPU related APIs
The patch defines below APIs :
cpu_is_hybrid_supported() : Check whether CPU is hybrid
CPU or not.
cpu_get_bus_frequency() : Get CPU's bus frequency
cpu_get_max_non_turbo_ratio() : Get CPU's max non-turbo ration
cpu_get_cpu_typ() : Get CPU type. The function must be called if executing
CPU is hybrid.
TEST=Verified the APIs on the Brya board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I680f43952ab4abce6e342206688ad32814970a91
---
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/include/intelblocks/cpulib.h
2 files changed, 69 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/59124/4
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59551 )
Change subject: drivers/i2c/tpm: Fix blank default statement
......................................................................
drivers/i2c/tpm: Fix blank default statement
CB:59479 introduced a blank default statement. This is treated as an
error or warning on some older toolchains. Add a break statement on
default case.
BUG=None
TEST=Build the Guybrush mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: I3d034cfebc8b8ae7d7024d41b4b2207cdeb083e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59551
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
Reviewed-by: Patrick Georgi <patrick(a)coreboot.org>
Reviewed-by: Rob Barnes <robbarnes(a)google.com>
---
M src/drivers/i2c/tpm/chip.c
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Georgi: Looks good to me, approved
Raul Rangel: Looks good to me, approved
Rob Barnes: Looks good to me, approved
diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c
index 3a2f8aa..07052f6 100644
--- a/src/drivers/i2c/tpm/chip.c
+++ b/src/drivers/i2c/tpm/chip.c
@@ -60,6 +60,7 @@
case TPM_DEFAULT_POWER_MANAGED:
default:
/* Leave firmware-power-managed unset */
+ break;
}
acpi_dp_write(dsd);
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