coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/elkhartlake: Disable Intel PSE by default
by Patrick Georgi (Code Review) 24 Nov '21

24 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59484 ) Change subject: soc/intel/elkhartlake: Disable Intel PSE by default ...................................................................... soc/intel/elkhartlake: Disable Intel PSE by default Disable PSE loading by default. If left enabled (current default), the EHL coreboot will end up in endless restart loop, due to FSP unable to locate PSE FW image and trigger global reset. However disabling this flag (PchPseEnable) will cause the coreboot to trigger a single reset due to CSE signal (HECI: CSE does not meet required prerequisites). The reason behind this is that FSP need to perform static disabling (power gate) to fully shut down PSE HW, and to do this will need to global reset entire system including CSE. Then PMC will power gate PSE from the start. To avoid this behavior, the best way to disable PSE is to disable via IFWI FIT softstrap (For specific detail can refer to Intel EHL coreboot MR2 release notes). With this, PMC will power gate PSE from the first cold boot and system will boot happily without single reset behavior. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Iccc0ab1c2e4ebb53013795933eb88262f70f456f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59484 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/elkhartlake/romstage/fsp_params.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index a15b030..ecb6304 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -123,6 +123,8 @@ config->ibecc.region_mask); } } + /* PSE (Intel Programmable Services Engine) switch */ + m_cfg->PchPseEnable = 0; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/59484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccc0ab1c2e4ebb53013795933eb88262f70f456f Gerrit-Change-Number: 59484 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [RFC]Documentation: Plan some depreciations / mandatory features
by Arthur Heymans (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59618 to review the following change. Change subject: [RFC]Documentation: Plan some depreciations / mandatory features ...................................................................... [RFC]Documentation: Plan some depreciations / mandatory features Some old codepaths are becoming rusty and a burden to the community, so it's best to migrate platforms to the newer codebase or depreciate them. When should this happen? After the 4.16 release? TODO: Have a discussion on the ML. Change-Id: I7dcf9343b999d435a3a1cdac6bb5f680ed02d388 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/releases/coreboot-4.16-relnotes.md 1 file changed, 65 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/59618/1 diff --git a/Documentation/releases/coreboot-4.16-relnotes.md b/Documentation/releases/coreboot-4.16-relnotes.md index 3c7eef2..c4f7070 100644 --- a/Documentation/releases/coreboot-4.16-relnotes.md +++ b/Documentation/releases/coreboot-4.16-relnotes.md @@ -1,7 +1,7 @@ Upcoming release - coreboot 4.16 ================================ -The 4.16 release is planned for Februrary, 2022. +The 4.16 release is planned for Februrary, 2022. We are increasing the frequency of releases in order to enable others to release quarterly on a fresher version of coreboot. @@ -16,4 +16,68 @@ Significant changes ------------------- +Deprecations +------------ + +The following deprecations are proposed: + +* RESOURCE_ALLOCATOR_V3 + rationale: The resource allocator v4 has been around for some time now + and there are patches on gerrit supporting backwards compatible behavior. +* LEGACY_SMP_INIT + rationale: parallel mp init is newer and has a better API which is quite flexible. + Supporting multiple AP init codepaths is a burden. Technically the parallel mp + init did not support SMM in ASEG but a POC was made and is on gerrit. + Migrating platforms to the parallel mp codepath should not be much work. + +Currently the following boards would be affected, however the proposed changes +could be implemented on all of these targets: + +AMD_INAGUA +AMD_OLIVEHILL +AMD_PARMER +AMD_SOUTHSTATION +AOPEN_DXPLPLUSU +AMD_PERSIMMON +AMD_THATCHER +AMD_UNIONSTATION +ASROCK_E350M1 +ASUS_A88XM_E +ASROCK_IMB_A180 +ASUS_AM1I_A +ASUS_F2A85_M +ASUS_F2A85_M_PRO +ASUS_F2A85_M_LE +ASUS_P2B_RAMDEBUG +ASUS_P2B_LS +ASUS_P2B_F +ASUS_P2B_D +ASUS_P2B_DS +ASUS_P3B_F +ASUS_P2B +ODE_E20XX +BIOSTAR_AM1ML +BIOSTAR_A68N5200 +ELMEX_PCM205400 +ELMEX_PCM205401 +GIZMOSPHERE_GIZMO2 +GIZMOSPHERE_GIZMO +HP_ABM +HP_PAVILION_M6_1035DX +JETWAY_NF81_T56N_LF +LENOVO_G505S +LIPPERT_FRONTRUNNER_AF +LIPPERT_TOUCAN_AF +MSI_MS7721 +PCENGINES_APU1_ +PCENGINES_APU2_ +PCENGINES_APU3_ +PCENGINES_APU4_ +PCENGINES_APU5_ +PCENGINES_APU1 +PCENGINES_APU2 +PCENGINES_APU3 +PCENGINES_APU4 +PCENGINES_APU5 + ### Add significant changes here -- To view, visit https://review.coreboot.org/c/coreboot/+/59618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7dcf9343b999d435a3a1cdac6bb5f680ed02d388 Gerrit-Change-Number: 59618 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: MAINTAINERS: Remove myself
by Patrick Georgi (Code Review) 24 Nov '21

24 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59490 ) Change subject: MAINTAINERS: Remove myself ...................................................................... MAINTAINERS: Remove myself Change-Id: Ic9dabd0386a32dd1ec0b99e0df3f41f34effc7a3 Signed-off-by: Patrick Georgi <patrick(a)georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59490 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M MAINTAINERS 1 file changed, 0 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index 0dcfca1..ecf836b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -231,13 +231,6 @@ -GETAC P470 MAINBOARD -M: Patrick Georgi <patrick(a)georgi.software> -S: Maintained -F: src/mainboard/getac/p470/ - - - GIGABYTE GA-D510UD MAINBOARD M: Angel Pons <th3fanbus(a)gmail.com> S: Maintained @@ -731,7 +724,6 @@ ################################################################################ ABUILD -M: Patrick Georgi <patrick(a)georgi-clan.de> M: Martin Roth <gaumless(a)gmail.com> S: Supported F: util/abuild/ @@ -740,7 +732,6 @@ F: util/board_status/ BUILD SYSTEM -M: Patrick Georgi <patrick(a)georgi-clan.de> M: Martin Roth <gaumless(a)gmail.com> S: Supported F: Makefile @@ -764,7 +755,6 @@ F: /util/gitconfig LINT SCRIPTS -M: Patrick Georgi <patrick(a)georgi-clan.de> M: Martin Roth <gaumless(a)gmail.com> S: Supported F: util/lint/ @@ -939,7 +929,6 @@ CODE OF CONDUCT M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> -M: Patrick Georgi <patrick(a)coreboot.org> M: Ronald Minnich <rminnich(a)coreboot.org> M: Martin Roth <martin(a)coreboot.org> S: Maintained -- To view, visit https://review.coreboot.org/c/coreboot/+/59490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9dabd0386a32dd1ec0b99e0df3f41f34effc7a3 Gerrit-Change-Number: 59490 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: MAINTAINERS: Remove myself
by Angel Pons (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Patrick Georgi. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59490 ) Change subject: MAINTAINERS: Remove myself ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9dabd0386a32dd1ec0b99e0df3f41f34effc7a3 Gerrit-Change-Number: 59490 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Comment-Date: Wed, 24 Nov 2021 11:09:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/cbmem_id.h: Add names for some IDs
by Felix Singer (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Angel Pons, Julius Werner. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59617 ) Change subject: commonlib/cbmem_id.h: Add names for some IDs ...................................................................... Patch Set 1: (1 comment) File src/commonlib/include/commonlib/cbmem_id.h: https://review.coreboot.org/c/coreboot/+/59617/comment/5c3783ae_3b09483d PS1, Line 107: CBMEM_ID_IGD_OPREGION > I imagine there used to be some order, but new additions ignored it completely. […] Nothing to do here :) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1033dd0cecff417b65001f25f6cc4101b603bd9b Gerrit-Change-Number: 59617 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 24 Nov 2021 11:06:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Angel Pons (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Nico Huber, Martin Roth, Mario Scheithauer, Lean Sheng Tan, Werner Zeh, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 56: (1 comment) File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/4d57188a_de1f8911 PS52, Line 129: /* Set the ownership of these devices to PSE */ : params->PchPseDmaEnable[0] = PSE_Owned; : params->PchPseUartEnable[2] = PSE_Owned; : params->PchPseHsuartEnable[2] = PSE_Owned; : params->PchPseI2cEnable[2] = PSE_Owned; : params->PchPseTimedGpioEnable[0] = PSE_Owned; : params->PchPseTimedGpioEnable[1] = PSE_Owned; : /* Disable PSE DMA Sideband Interrupt for DMA 0 */ : params->PchPseDmaSbInterruptEnable[0] = 0; : /* Set the log output to PSE UART 2 */ : params->PchPseLogOutputChannel = 3; > Hi Angel, sorry I cannot do much about it for now :( PSE requires these configs to work properly. […] No worries, thanks for your time. I'm OK with leaving this as-is for now, but it would be great to properly address this in the future. -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 56 Gerrit-Owner: Lean Sheng Tan Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 24 Nov 2021 11:03:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/cbmem_id.h: Add names for some IDs
by Angel Pons (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Felix Singer, Julius Werner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59617 ) Change subject: commonlib/cbmem_id.h: Add names for some IDs ...................................................................... Patch Set 1: (1 comment) File src/commonlib/include/commonlib/cbmem_id.h: https://review.coreboot.org/c/coreboot/+/59617/comment/ca0551a6_bed97842 PS1, Line 107: CBMEM_ID_IGD_OPREGION > Just wondering, do these entries have any specific order? Seems pretty random. I imagine there used to be some order, but new additions ignored it completely. My main concern is whether these IDs purposely had no name. Anything to do here, or can I mark this as resolved? -- To view, visit https://review.coreboot.org/c/coreboot/+/59617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1033dd0cecff417b65001f25f6cc4101b603bd9b Gerrit-Change-Number: 59617 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 24 Nov 2021 11:01:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Disable Intel PSE by default
by Felix Singer (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Lean Sheng Tan, Michael Niewöhner, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59484 ) Change subject: soc/intel/elkhartlake: Disable Intel PSE by default ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccc0ab1c2e4ebb53013795933eb88262f70f456f Gerrit-Change-Number: 59484 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 24 Nov 2021 11:00:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/cbmem_id.h: Add names for some IDs
by Felix Singer (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Angel Pons, Julius Werner. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59617 ) Change subject: commonlib/cbmem_id.h: Add names for some IDs ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/commonlib/include/commonlib/cbmem_id.h: https://review.coreboot.org/c/coreboot/+/59617/comment/9eb483fb_edf80fcd PS1, Line 107: CBMEM_ID_IGD_OPREGION Just wondering, do these entries have any specific order? Seems pretty random. -- To view, visit https://review.coreboot.org/c/coreboot/+/59617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1033dd0cecff417b65001f25f6cc4101b603bd9b Gerrit-Change-Number: 59617 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 24 Nov 2021 10:58:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/cbmem_id.h: Fix typo in macro name
by Felix Singer (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Angel Pons, Julius Werner, Arthur Heymans, Patrick Rudolph, Tim Chu. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59616 ) Change subject: commonlib/cbmem_id.h: Fix typo in macro name ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e680244c9573f566b51298462c324e062ab4657 Gerrit-Change-Number: 59616 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 24 Nov 2021 10:57:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021