coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/elkhartlake: Disable Intel PSE by default
by Werner Zeh (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Lean Sheng Tan, Michael Niewöhner, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59484 ) Change subject: soc/intel/elkhartlake: Disable Intel PSE by default ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: Since this was requested but lacks reviewers I give it a +2 now. -- To view, visit https://review.coreboot.org/c/coreboot/+/59484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccc0ab1c2e4ebb53013795933eb88262f70f456f Gerrit-Change-Number: 59484 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 24 Nov 2021 10:52:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/cbmem_id.h: Add names for some IDs
by Angel Pons (Code Review) 24 Nov '21

24 Nov '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59617 ) Change subject: commonlib/cbmem_id.h: Add names for some IDs ...................................................................... commonlib/cbmem_id.h: Add names for some IDs Some IDs don't have an associated name. Add them. Change-Id: I1033dd0cecff417b65001f25f6cc4101b603bd9b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/commonlib/include/commonlib/cbmem_id.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/59617/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 5c90537..d150811 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -104,8 +104,10 @@ { CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \ { CBMEM_ID_GDT, "GDT " }, \ { CBMEM_ID_HOB_POINTER, "HOB " }, \ + { CBMEM_ID_IGD_OPREGION, "IGD OPREGION" }, \ { CBMEM_ID_IMD_ROOT, "IMD ROOT " }, \ { CBMEM_ID_IMD_SMALL, "IMD SMALL " }, \ + { CBMEM_ID_MDATA_HASH, "METADATA HASH" }, \ { CBMEM_ID_MEMINFO, "MEM INFO " }, \ { CBMEM_ID_MMA_DATA, "MMA DATA " }, \ { CBMEM_ID_MMC_STATUS, "MMC STATUS " }, \ @@ -133,6 +135,7 @@ { CBMEM_ID_TCPA_TCG_LOG, "TCPA TCGLOG" }, \ { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \ { CBMEM_ID_TPM2_TCG_LOG, "TPM2 TCGLOG" }, \ + { CBMEM_ID_TPM_PPI, "TPM PPI " }, \ { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \ { CBMEM_ID_VBOOT_SEL_REG, "VBOOT SEL " }, \ { CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \ @@ -147,5 +150,7 @@ { CBMEM_ID_FMAP, "FMAP "}, \ { CBMEM_ID_CBFS_RO_MCACHE, "RO MCACHE "}, \ { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}, \ + { CBMEM_ID_FSP_LOGO, "FSP LOGO "}, \ + { CBMEM_ID_SMM_COMBUFFER, "SMM COMBUFFER"}, \ { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"} #endif /* _CBMEM_ID_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1033dd0cecff417b65001f25f6cc4101b603bd9b Gerrit-Change-Number: 59617 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: commonlib/cbmem_id.h: Fix typo in macro name
by Angel Pons (Code Review) 24 Nov '21

24 Nov '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59616 ) Change subject: commonlib/cbmem_id.h: Fix typo in macro name ...................................................................... commonlib/cbmem_id.h: Fix typo in macro name Rename `CMBMEM_ID_ACPI_HEST` to `CBMEM_ID_ACPI_HEST`. Change-Id: I3e680244c9573f566b51298462c324e062ab4657 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/commonlib/include/commonlib/cbmem_id.h M src/soc/intel/xeon_sp/ras/hest.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/59616/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index a9cf7bd..5c90537 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -7,7 +7,7 @@ #define CBMEM_ID_ACPI_BERT 0x42455254 #define CBMEM_ID_ACPI_CNVS 0x434e5653 #define CBMEM_ID_ACPI_GNVS 0x474e5653 -#define CMBMEM_ID_ACPI_HEST 0x48455354 +#define CBMEM_ID_ACPI_HEST 0x48455354 #define CBMEM_ID_ACPI_UCSI 0x55435349 #define CBMEM_ID_AFTER_CAR 0xc4787a93 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 @@ -85,7 +85,7 @@ { CBMEM_ID_ACPI_BERT, "ACPI BERT " }, \ { CBMEM_ID_ACPI_CNVS, "CHROMEOS NVS" }, \ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ - { CMBMEM_ID_ACPI_HEST, "ACPI HEST " }, \ + { CBMEM_ID_ACPI_HEST, "ACPI HEST " }, \ { CBMEM_ID_ACPI_UCSI, "ACPI UCSI " }, \ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ { CBMEM_ID_AFTER_CAR, "AFTER CAR " }, \ diff --git a/src/soc/intel/xeon_sp/ras/hest.c b/src/soc/intel/xeon_sp/ras/hest.c index 6164edf..02a9ab1 100644 --- a/src/soc/intel/xeon_sp/ras/hest.c +++ b/src/soc/intel/xeon_sp/ras/hest.c @@ -75,7 +75,7 @@ acpi_hest_t *hest; /* Reserve memory for Enhanced error logging */ - void *mem = cbmem_add(CMBMEM_ID_ACPI_HEST, CONFIG_ERROR_LOG_BUFFER_SIZE); + void *mem = cbmem_add(CBMEM_ID_ACPI_HEST, CONFIG_ERROR_LOG_BUFFER_SIZE); if (!mem) { printk(BIOS_ERR, "Unable to allocate HEST memory\n"); return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/59616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e680244c9573f566b51298462c324e062ab4657 Gerrit-Change-Number: 59616 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: timestamp: Add new helper functions
by Subrata Banik (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Tim Wawrzynczak, Angel Pons, Julius Werner, Aaron Durbin. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51445 ) Change subject: timestamp: Add new helper functions ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51445/comment/032076ad_6c28fe35 PS3, Line 7: Add helper fucntions > > Thanks Angel and Julius for your suggestion. I believe we all are in same page but we are using different notation to explain our understanding. > > > > Let me put the question straight here: > > > > if you take a look into below table, the timestamp ids are in serialized order where > > ``` > > 944: CSE sent boot stall done to PMC is the first activity for CSE RO post coming out from reset. > > > > Followed by > > > > 945, 946 and finally 947 where CSE receives CPU reset ack from PMC and we are moving towards CPU coming out from reset > > ``` > > Yes, makes sense. > > > now if we subtract the CSE timestamp from base or `0` and the cbmem does its sorting, it breaks the pre-cpu reset order (as you can see below, 947 becoming the least negative number). > > If I understand you correctly, does "least negative number" mean the same as "negative number with the smallest absolute value"? For example, the "least negative number" among { -6, -3, -4 } would be -3, right? Or am I misunderstanding you? "negative number with the largest absolute value" i meant like in above example: `(-1,074,000)` "947:CSE received 'CPU Reset Done Ack sent' from PMC" is the least entry for cbmem table. > > If my interpretation is correct, I don't see what the problem is. 947 is the last event that happened before the "1st timestamp", so it should be the "least negative number". AIUI, the result should be something like this: > > 944:CSE sent 'Boot Stall Done' to PMC -1,074,000 (18,483,711,496,695,957) > 945:CSE started to handle ICC configuration -308,000 (18,483,711,496,697,957) > 946:CSE sent 'Host BIOS Prep Done' to PMC -303,000 (18,483,711,495,936,957) > 947:CSE received 'CPU Reset Done Ack sent' from PMC -296,000 > 0:1st timestamp 0 > Here is the data that we have extracted from CSE and as per that data. 944: CSE sent 'Boot Stall Done' to PMC takes 296ms 945: CSE started to handle ICC configuration takes ~7ms 946: CSE sent 'Host BIOS Prep Done' to PMC takes ~5ms 947: CSE received 'CPU Reset Done Ack sent' from PMC takes ~766ms hence, if we put those in order with assumption that while power-on the 1st time stamp is 0 then all above data appear as per below order: 0:1st timestamp 0 944:CSE sent 'Boot Stall Done' to PMC 296,000 945:CSE started to handle ICC configuration 303,000 (7,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 308,000 (5,000) 947:CSE received 'CPU Reset Done Ack sent' from PMC 1,074,000 (766,000) Now, after 1sec (1,074ms/1,074,000ns) post reset, CPU would come out from the reset. Consider timestamp id 11 as "Start of Bootblock" is first time stamp that comes coreboot bootblock takes ~27sec then now the entire table should look as below: 0:1st timestamp 0 944:CSE sent 'Boot Stall Done' to PMC 296,000 945:CSE started to handle ICC configuration 303,000 (7,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 308,000 (5,000) 947:CSE received 'CPU Reset Done Ack sent' from PMC 1,074,000 (766,000) 11:start of bootblock 1,101,606 (27,606) Do you agree with this ? Having negative number is the calculation would look only perfect as @Bora has mentioned below, he need to perform an additional qsort to move "timestamp id: 947" elapse value into order rather appearing at the first entry which is not correct as per the CSE reset flow. > Hmmm, but timestamps currently use unsigned integers. I guess that's why the numbers in parentheses are so large, they underflow. > > > This is what my concern was about. I believe subtract is the final solution for simplicity but followed by sorting makes it weird as below. > > > > 0:1st timestamp 0 > > 947:CSE received 'CPU Reset Done Ack sent' from PMC 1,074,000 > > 946:CSE sent 'Host BIOS Prep Done' to PMC 308,000 (18,483,711,495,936,957) > > 945:CSE started to handle ICC configuration 303,000 (18,483,711,496,697,957) > > 944:CSE sent 'Boot Stall Done' to PMC 296,000 (18,483,711,496,695,957) > > Yes, I agree this ordering looks very weird. -- To view, visit https://review.coreboot.org/c/coreboot/+/51445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7065ed26e231fc898ae44bcc15cba6fb42b308 Gerrit-Change-Number: 51445 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 24 Nov 2021 10:47:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: timestamp: Add new helper functions
by Angel Pons (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Tim Wawrzynczak, Subrata Banik, Julius Werner, Aaron Durbin. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51445 ) Change subject: timestamp: Add new helper functions ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51445/comment/95685d8c_7565957b PS3, Line 7: Add helper fucntions > Thanks Angel and Julius for your suggestion. I believe we all are in same page but we are using different notation to explain our understanding. > > Let me put the question straight here: > > if you take a look into below table, the timestamp ids are in serialized order where > ``` > 944: CSE sent boot stall done to PMC is the first activity for CSE RO post coming out from reset. > > Followed by > > 945, 946 and finally 947 where CSE receives CPU reset ack from PMC and we are moving towards CPU coming out from reset > ``` Yes, makes sense. > now if we subtract the CSE timestamp from base or `0` and the cbmem does its sorting, it breaks the pre-cpu reset order (as you can see below, 947 becoming the least negative number). If I understand you correctly, does "least negative number" mean the same as "negative number with the smallest absolute value"? For example, the "least negative number" among { -6, -3, -4 } would be -3, right? Or am I misunderstanding you? If my interpretation is correct, I don't see what the problem is. 947 is the last event that happened before the "1st timestamp", so it should be the "least negative number". AIUI, the result should be something like this: 944:CSE sent 'Boot Stall Done' to PMC -1,074,000 (18,483,711,496,695,957) 945:CSE started to handle ICC configuration -308,000 (18,483,711,496,697,957) 946:CSE sent 'Host BIOS Prep Done' to PMC -303,000 (18,483,711,495,936,957) 947:CSE received 'CPU Reset Done Ack sent' from PMC -296,000 0:1st timestamp 0 Hmmm, but timestamps currently use unsigned integers. I guess that's why the numbers in parentheses are so large, they underflow. > This is what my concern was about. I believe subtract is the final solution for simplicity but followed by sorting makes it weird as below. > > 0:1st timestamp 0 > 947:CSE received 'CPU Reset Done Ack sent' from PMC 1,074,000 > 946:CSE sent 'Host BIOS Prep Done' to PMC 308,000 (18,483,711,495,936,957) > 945:CSE started to handle ICC configuration 303,000 (18,483,711,496,697,957) > 944:CSE sent 'Boot Stall Done' to PMC 296,000 (18,483,711,496,695,957) Yes, I agree this ordering looks very weird. -- To view, visit https://review.coreboot.org/c/coreboot/+/51445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7065ed26e231fc898ae44bcc15cba6fb42b308 Gerrit-Change-Number: 51445 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 24 Nov 2021 10:26:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Add DPTF parameters for Felwinter
by John Su (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Tim Wawrzynczak, Sumeet R Pawnikar, Felix Held. John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59614 ) Change subject: mb/google/brya/var/felwinter: Add DPTF parameters for Felwinter ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/brya/variants/felwinter/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59614/comment/f43bd34b_a7d85bd9 PS3, Line 97: 39000 > Confirm from our thermal team and change setting. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I634d6d98c28e75ad41488921df6b8e836e253ff1 Gerrit-Change-Number: 59614 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 24 Nov 2021 10:17:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: John Su <john_su(a)compal.corp-partner.google.com> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Add DPTF parameters for Felwinter
by John Su (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Tim Wawrzynczak, Sumeet R Pawnikar, Felix Held. John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59614 ) Change subject: mb/google/brya/var/felwinter: Add DPTF parameters for Felwinter ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/brya/variants/felwinter/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59614/comment/8421278a_242a4a13 PS3, Line 97: 39000 > Normally we set min and max power values same for pl2. Set this to 55000. Confirm from our thermal team and change setting. -- To view, visit https://review.coreboot.org/c/coreboot/+/59614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I634d6d98c28e75ad41488921df6b8e836e253ff1 Gerrit-Change-Number: 59614 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 24 Nov 2021 10:16:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Add DPTF parameters for Felwinter
by John Su (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: John Su, Tim Wawrzynczak, Felix Held. Hello build bot (Jenkins), Tim Wawrzynczak, Sumeet R Pawnikar, EricR Lai, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59614 to look at the new patch set (#4). Change subject: mb/google/brya/var/felwinter: Add DPTF parameters for Felwinter ...................................................................... mb/google/brya/var/felwinter: Add DPTF parameters for Felwinter DPTF paramerters from thermal team. BUG=b:207463762 BRANCH=brya TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I634d6d98c28e75ad41488921df6b8e836e253ff1 --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 96 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/59614/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I634d6d98c28e75ad41488921df6b8e836e253ff1 Gerrit-Change-Number: 59614 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Nico Huber, Martin Roth, Mario Scheithauer, Werner Zeh, Felix Held. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 56: (1 comment) File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/db7d6eb3_6f931713 PS55, Line 94: printk(BIOS_DEBUG, "PSE base: %08x size: %08zx\n", : pse_fw_base, psefwsize); > This do fit on one line now. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 56 Gerrit-Owner: Lean Sheng Tan Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 24 Nov 2021 10:11:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 24 Nov '21

24 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Martin Roth, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55367 to look at the new patch set (#56). Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... soc/intel/elkhartlake: Introduce Intel PSE The Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization. The PSE hosts new functions, including remote out-of-band device management, network proxy, embedded controller lite and sensor hub. This CL enables the user to provide the base address of the PSE FW blob which will then be loaded by the FSP-S onto the ARM controller. PSE FW will do the initialization work of PSE controller and its peripherals. The loading of PSE FW should have negligible impact on boot time unless PSE controller could not locate the PSE FW and FSP will attempt to redo PSE FW loading and wait for PSE handshake until it times out. Once PSE controller locate the PSE FW, it will do initialization concurrently by itself with coreboot booting. It also adds PSE related FSP-S UPD settings which enable the setup of peripheral ownership (assigned to the PSE or x86 subsystem) and interrupts. These assignments need to take place at a given point in the boot process and cannot be changed later. To verify if PSE FW is loaded properly, the user could enable PchPseShellEnabled flag and the log will be printed at PSE UART 2. For further info please refer to doc #611825 (for HW overview) and #614110 (for PSE EDS). Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/elkhartlake/romstage/fsp_params.c 5 files changed, 171 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/55367/56 -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 56 Gerrit-Owner: Lean Sheng Tan Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021