Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59630 )
Change subject: soc/amd/common/block/include/gpio_defs: rework de-glitching defines
......................................................................
soc/amd/common/block/include/gpio_defs: rework de-glitching defines
I found the name of the DEB_GLITCH_NONE definition a bit misleading, so
change it to DEB_GLITCH_REMOVE which should clarify what this will do.
The description for this value in the PPR/BKDG is "Remove glitch". This
also puts the define in line with GPIO_DEB_REMOVE_GLITCH which is the
only place where DEB_GLITCH_NONE/DEB_GLITCH_REMOVE is used.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I59648710e0ff28c2026e1b2cc7e433cafb2f2807
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59630
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
---
M src/soc/amd/common/block/include/amdblocks/gpio_defs.h
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Marshall Dawson: Looks good to me, approved
diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h
index 0422079..1e3b172 100644
--- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h
+++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h
@@ -105,10 +105,10 @@
#define DEB_GLITCH_SHIFT 5
#define DEB_GLITCH_LOW 1
#define DEB_GLITCH_HIGH 2
-#define DEB_GLITCH_NONE 3
+#define DEB_GLITCH_REMOVE 3
#define GPIO_DEB_PRESERVE_LOW_GLITCH (DEB_GLITCH_LOW << DEB_GLITCH_SHIFT)
#define GPIO_DEB_PRESERVE_HIGH_GLITCH (DEB_GLITCH_HIGH << DEB_GLITCH_SHIFT)
-#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_NONE << DEB_GLITCH_SHIFT)
+#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_REMOVE << DEB_GLITCH_SHIFT)
#define GPIO_TIMEBASE_61uS 0
#define GPIO_TIMEBASE_183uS (1 << 4)
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Subrata Banik has uploaded a new patch set (#3) to the change originally created by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/56652 )
Change subject: soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig
......................................................................
soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig
This patch helps to save ~20ms of booting time without
any issue seen during MP Init. All cores are out from
reset and alive.
Additionally, no performance degradation is observed while
running benchmarks.
Change-Id: I4a358409beb18fc2517020fae88f528b58ab3907
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/56652/3
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Subrata Banik has uploaded a new patch set (#4) to the change originally created by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/56651 )
Change subject: cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_NEED_1_SIPI
......................................................................
cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_NEED_1_SIPI
This patch renames X86_AMD_INIT_SIPI Kconfig to leverage
the same logic (to skip 2nd SIPI and reduce delay between
INIT and SIPI while perform AP initialization) even on
newer Intel platform.
Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/cpu/x86/Kconfig
M src/cpu/x86/mp_init.c
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/picasso/Kconfig
4 files changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/56651/4
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56651 )
Change subject: cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_SIPI
......................................................................
Patch Set 3:
(2 comments)
File src/cpu/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/56651/comment/33d3cfad_19a436ec
PS3, Line 174: and SIPI,
> nit: wrap on the next line.
Ack
File src/cpu/x86/mp_init.c:
https://review.coreboot.org/c/coreboot/+/56651/comment/7e8f2a7b_d0933068
PS3, Line 472: X86_INIT_SIPI
> maybe use a more descriptive name: X86_INIT_NEED_1_SIPI
Ack
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56093 )
Change subject: mb/google/herobrine: Initialize USB by calling SOC method
......................................................................
Patch Set 40: Code-Review+1
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59195 )
Change subject: soc: Add dram information to cbmem
......................................................................
Patch Set 5:
(4 comments)
File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/59195/comment/be73372c_732616b5
PS5, Line 26: static void write_mem_chip_information(struct qclib_cb_if_table_entry *te);
static functions don't need a prototype.
https://review.coreboot.org/c/coreboot/+/59195/comment/d67246f4_7f512041
PS5, Line 37:
There should be some kind of check here to make sure the data was actually filled out (e.g. mem_chip_size != 0 or something, if that works). It can be an assert() if we make sure that both sc7180 and sc7280 qclib will support this before this patch is merged.
https://review.coreboot.org/c/coreboot/+/59195/comment/98c39176_5e572701
PS5, Line 40: ASSERT(mem_region_base != NULL);
nit: can just write
assert(cbmem_add(...) != NULL);
to be shorter.
https://review.coreboot.org/c/coreboot/+/59195/comment/f0632188_827de64c
PS5, Line 174: mem_chip_info
This pointer is still NULL here, how is this supposed to work? The global variable needs to be an actual backing buffer, not just a pointer.
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