coreboot-gerrit November 2021

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Change in coreboot[master]: payloads/U-Boot: Tidy up the U-Boot build
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59600 ) Change subject: payloads/U-Boot: Tidy up the U-Boot build ...................................................................... payloads/U-Boot: Tidy up the U-Boot build This doesn't work at present, merely printing an error when U-Boot is selected as a payload. This is because it adds a file into the U-Boot tree which makes U-Boot's build system think that the tree is unclean. Update the rules to put the tag file outside the source tree. Use an out-of-tree build for U-Boot to avoid changing the source tree. Signed-off-by: Simon Glass <sjg(a)chromium.org> Change-Id: I24d6545b54f97afeefaca3ffed79eec2e7afacb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59600 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/Makefile.inc M payloads/external/U-Boot/Kconfig M payloads/external/U-Boot/Makefile 3 files changed, 13 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 6db1720..151a27c 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -197,7 +197,7 @@ # U-Boot -payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot: $(DOTCONFIG) +payloads/external/U-Boot/build/u-boot/u-boot-dtb.bin u-boot: $(DOTCONFIG) $(MAKE) -C payloads/external/U-Boot \ CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \ CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE) diff --git a/payloads/external/U-Boot/Kconfig b/payloads/external/U-Boot/Kconfig index 9e51ae1..b635bbb 100644 --- a/payloads/external/U-Boot/Kconfig +++ b/payloads/external/U-Boot/Kconfig @@ -32,7 +32,7 @@ from the U-Boot config directory config PAYLOAD_FILE - default "payloads/external/U-Boot/u-boot/u-boot-dtb.bin" + default "payloads/external/U-Boot/build/u-boot/u-boot-dtb.bin" config PAYLOAD_OPTIONS default "-l 0x1110000 -e 0x1110015" diff --git a/payloads/external/U-Boot/Makefile b/payloads/external/U-Boot/Makefile index 38dfe99..1d1d332 100644 --- a/payloads/external/U-Boot/Makefile +++ b/payloads/external/U-Boot/Makefile @@ -9,7 +9,10 @@ project_name=U-Boot project_dir=u-boot project_git_repo=http://git.denx.de/u-boot.git -project_config_file=$(project_dir)/.config +project_build_dir=build +project_config_file=$(project_build_dir)/.config + +make_args=-C $(project_dir) O=../build unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG @@ -31,11 +34,11 @@ git fetch #master doesn't get a file, so it's continuously updated - rm -f $(project_dir)/$(STABLE_COMMIT_ID) + rm -f $(STABLE_COMMIT_ID) else cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ then echo " Fetching new commits from the $(project_name) git repo"; git fetch; fi - touch $(project_dir)/$(STABLE_COMMIT_ID) + touch $(STABLE_COMMIT_ID) endif checkout: fetch @@ -43,26 +46,26 @@ cd $(project_dir); git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) config: checkout + mkdir -p $(project_build_dir) rm -f $(project_config_file) ifneq ($(CONFIG_PAYLOAD_CONFIGFILE),) ifneq ("$(wildcard $(CONFIG_PAYLOAD_CONFIGFILE))","") cat $(CONFIG_PAYLOAD_CONFIGFILE)" > tag-$(project_config_file) + $(MAKE) $(make_args) olddefconfig else echo "Error: File $(CONFIG_PAYLOAD_CONFIGFILE) does not exist" false endif else - cat $(project_dir)/configs/coreboot_defconfig >> $(project_config_file) + $(MAKE) $(make_args) coreboot_defconfig endif - $(MAKE) -C $(project_dir) olddefconfig - build: config echo " MAKE $(project_name) $(TAG-y)" - $(MAKE) -C $(project_dir) + $(MAKE) $(make_args) clean: - test -d $(project_dir) && $(MAKE) -C $(project_dir) clean || exit 0 + test -d $(project_dir) && $(MAKE) $(make_args) clean || exit 0 distclean: rm -rf $(project_dir) -- To view, visit https://review.coreboot.org/c/coreboot/+/59600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24d6545b54f97afeefaca3ffed79eec2e7afacb4 Gerrit-Change-Number: 59600 Gerrit-PatchSet: 2 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/dell/optiplex_9010/romstage.c: Add interrupt routing map
by Michał Żygowski (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Paul Menzel, Angel Pons, Felix Held. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59525 ) Change subject: mb/dell/optiplex_9010/romstage.c: Add interrupt routing map ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59525/comment/e129afad_a4df5d02 PS3, Line 9: Dumped from the Dell BIOS version A30. > If you can give the used command or how you did it, that would be great. I simply used the logs from inteltool and replicated the registers contents. Added to the commit message. Patchset: PS3: > Does the new routing improve anything? When enabling TXT I had problems with GbE reported as uninitialized and I thought I may be lacking the routing. Later it occurred this was not the case, but the work was already done so I thought at least I can push it. -- To view, visit https://review.coreboot.org/c/coreboot/+/59525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdc41a1e6627b68813fb264aed7e30df58fc6d54 Gerrit-Change-Number: 59525 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 25 Nov 2021 21:03:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/dell/optiplex_9010/romstage.c: Add interrupt routing map
by Michał Żygowski (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski, Felix Held. Hello build bot (Jenkins), Paul Menzel, Angel Pons, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59525 to look at the new patch set (#4). Change subject: mb/dell/optiplex_9010/romstage.c: Add interrupt routing map ...................................................................... mb/dell/optiplex_9010/romstage.c: Add interrupt routing map Dumped using inteltool from the Dell BIOS version A30. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ifdc41a1e6627b68813fb264aed7e30df58fc6d54 --- M src/mainboard/dell/optiplex_9010/romstage.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/59525/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdc41a1e6627b68813fb264aed7e30df58fc6d54 Gerrit-Change-Number: 59525 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: superio/smsc/sch5545: Disable PS/2 lines isolation during init
by Angel Pons (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59673 ) Change subject: superio/smsc/sch5545: Disable PS/2 lines isolation during init ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac6be095c996b357b5d4e8d75199f94a89bf73e9 Gerrit-Change-Number: 59673 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 25 Nov 2021 20:59:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: superio/smsc/sch5545: Clear PMEs in the early init
by Angel Pons (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59524 ) Change subject: superio/smsc/sch5545: Clear PMEs in the early init ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I790cac3ce1101565b64ed54d9c6b50f5e9aa4cf6 Gerrit-Change-Number: 59524 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 25 Nov 2021 20:59:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: superio/smsc/sch5545: Clear PMEs in the early init
by Michał Żygowski (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Angel Pons, Felix Held. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59524 ) Change subject: superio/smsc/sch5545: Clear PMEs in the early init ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59524/comment/2576c398_759ba70d PS3, Line 17: be always > nit: `always be` Moved to patch CB:59673 and fixed there. Patchset: PS3: > i would have done the two logical changes as separate patches, but i'm ok with either way Separated the keyboard patch CB:59673 File src/superio/smsc/sch5545/superio.c: https://review.coreboot.org/c/coreboot/+/59524/comment/d8fb9ff4_57f2f053 PS3, Line 68: pnp_write_config(dev, 0xf0, pnp_read_config(dev, 0xf0) & 0x9f); > How about: […] Applied in patch CB:59673 -- To view, visit https://review.coreboot.org/c/coreboot/+/59524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I790cac3ce1101565b64ed54d9c6b50f5e9aa4cf6 Gerrit-Change-Number: 59524 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 25 Nov 2021 20:56:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59676 ) Change subject: soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80 ...................................................................... soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80 When using 32 bit PCI accesses in lpc_enable_port80, we can use the LPC_IO_OR_MEM_DECODE_ENABLE and DECODE_IO_PORT_ENABLE4 defines and don't need to re-define bits with offsets from the beginning of the third byte within this 32 bit register. This allows to drop the LPC_IO_OR_MEM_DEC_EN_HIGH register definition which points to LPC_IO_OR_MEM_DECODE_ENABLE + 2 and to drop the re-definitions of the bit re-definitions with a different offset. The code in lpc_enable_port80 was originally copied from sb/amd/agesa/ hudson/early_setup.c which might be sort-of a copy from what the AGESA reference code does. TEST=When commenting out SOC_AMD_COMMON_BLOCK_USE_ESPI in the Kconfig of Mandolin and selecting AMD_LPC_DEBUG_CARD, all POST codes still get shown on the POST code LED display when this patch is applied. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I001bb1c2ccf99e36d4fbd73d3bf96b78ddb87d67 --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/lpc_util.c 2 files changed, 4 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59676/1 diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 44a0c02..173cbd1 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -69,18 +69,6 @@ #define LPC_SELECT_SIO_2E2F 0 #define WIDEIO_RANGE_ERROR -1 -/* Assuming word access to higher word (register 0x4a) */ -#define LPC_IO_OR_MEM_DEC_EN_HIGH 0x4a -#define LPC_WIDEIO2_ENABLE_H BIT(9) -#define LPC_WIDEIO1_ENABLE_H BIT(8) -#define DECODE_IO_PORT_ENABLE6_H BIT(7) -#define DECODE_IO_PORT_ENABLE5_H BIT(6) -#define DECODE_IO_PORT_ENABLE4_H BIT(5) -#define DECODE_IO_PORT_ENABLE3_H BIT(3) -#define DECODE_IO_PORT_ENABLE2_H BIT(2) -#define DECODE_IO_PORT_ENABLE1_H BIT(1) -#define DECODE_IO_PORT_ENABLE0_H BIT(0) - #define LPC_MEM_PORT1 0x4c #define ROM_PROTECT_RANGE0 0x50 #define ROM_BASE_MASK 0xfffff000 /* bits 31-12 */ diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index c40a198..7291959 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -138,11 +138,11 @@ void lpc_enable_port80(void) { - u8 byte; + uint32_t tmp; - byte = pci_read_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); - byte |= DECODE_IO_PORT_ENABLE4_H; - pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); + tmp = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + tmp |= DECODE_IO_PORT_ENABLE4; + pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, tmp); } void lpc_enable_sio_decode(const bool addr) -- To view, visit https://review.coreboot.org/c/coreboot/+/59676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I001bb1c2ccf99e36d4fbd73d3bf96b78ddb87d67 Gerrit-Change-Number: 59676 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/lpc/lpc_util: drop lpc_enable_pci_port80
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59675 ) Change subject: soc/amd/common/block/lpc/lpc_util: drop lpc_enable_pci_port80 ...................................................................... soc/amd/common/block/lpc/lpc_util: drop lpc_enable_pci_port80 This function is unused and none of the SoCs using this code has a physical PCI interface any more, so drop this function. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia5c5a8ec29264a075fefe75038ef2a84684d6427 --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/lpc_util.c 2 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/59675/1 diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 7c798d6..44a0c02 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -144,7 +144,6 @@ * with the enable bits. */ void lpc_disable_decodes(void); void lpc_enable_port80(void); -void lpc_enable_pci_port80(void); void lpc_enable_decode(uint32_t decodes); /* addr = index/data to enable: LPC_SELECT_SIO_2E2F or LPC_SELECT_SIO_4E4F */ void lpc_enable_sio_decode(const bool addr); diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index fb231dd..c40a198 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -145,15 +145,6 @@ pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); } -void lpc_enable_pci_port80(void) -{ - u8 byte; - - byte = pci_read_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); - byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */ - pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); -} - void lpc_enable_sio_decode(const bool addr) { uint32_t decodes; -- To view, visit https://review.coreboot.org/c/coreboot/+/59675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5c5a8ec29264a075fefe75038ef2a84684d6427 Gerrit-Change-Number: 59675 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59674 ) Change subject: soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs ...................................................................... soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs Both SPI_ROM_BIOS_SEMAPHORE and SPI_ROM_EC_SEMAPHORE bits in the LPC_PCI_CONTROL are defined in the Stoneyridge BKDG #55072 Rev 3.04, Raven1 and Picasso PPR #55570 Rev 3.18, Raven2 PPR #55772 Rev 3.08 and Cezanne PPR #56569 Rev 3.03 which are all platforms that use this code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575 --- M src/soc/amd/common/block/include/amdblocks/lpc.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/59674/1 diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 09eafb8..7c798d6 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -10,6 +10,8 @@ #define LEGACY_DMA_EN BIT(2) #define VW_ROM_SHARING_EN BIT(3) #define EXT_ROM_SHARING_EN BIT(4) +#define SPI_ROM_BIOS_SEMAPHORE BIT(5) +#define SPI_ROM_EC_SEMAPHORE BIT(6) #define LPC_IO_PORT_DECODE_ENABLE 0x44 #define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) -- To view, visit https://review.coreboot.org/c/coreboot/+/59674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575 Gerrit-Change-Number: 59674 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/smsc/sch5545: Disable PS/2 lines isolation during init
by Michał Żygowski (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Felix Held. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59673 ) Change subject: superio/smsc/sch5545: Disable PS/2 lines isolation during init ...................................................................... superio/smsc/sch5545: Disable PS/2 lines isolation during init Disable PS/2 data and clock isolation in order to properly initialize the PS/2 keyboard and mouse in payload/OS. These bits are set by OS via ACPI and can survive S5 state. It is necessary to clear them after an ungraceful shutdown in order to perform PS/2 controller initialization e.g. in SeaBIOS. TEST=PS/2 keyboard can always be successfully initialized in SeaBIOS on Dell OptiPlex 9010 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Iac6be095c996b357b5d4e8d75199f94a89bf73e9 --- M src/superio/smsc/sch5545/superio.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/59673/1 diff --git a/src/superio/smsc/sch5545/superio.c b/src/superio/smsc/sch5545/superio.c index b6e5308..2fe5d03 100644 --- a/src/superio/smsc/sch5545/superio.c +++ b/src/superio/smsc/sch5545/superio.c @@ -62,6 +62,12 @@ switch (dev->path.pnp.device) { case SCH5545_LDN_KBC: + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + /* Disable PS/2 clock and data isolation */ + pnp_unset_and_set_config(dev, 0xf0, + SCH5545_KBD_ISOLATION | SCH5545_MOUSE_ISOLATION, 0); + pnp_exit_conf_mode(dev); pc_keyboard_init(NO_AUX_DEVICE); break; case SCH5545_LDN_LPC: -- To view, visit https://review.coreboot.org/c/coreboot/+/59673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac6be095c996b357b5d4e8d75199f94a89bf73e9 Gerrit-Change-Number: 59673 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021