coreboot-gerrit October 2021

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Change in coreboot[master]: tests: Add lib/lzma-test test case
by Paul Fagerburg (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Jakub Czapiga, Jan Dabros. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57555 ) Change subject: tests: Add lib/lzma-test test case ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id75e0b41991382d4c391b031862106de58eacdf7 Gerrit-Change-Number: 57555 Gerrit-PatchSet: 7 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Thu, 07 Oct 2021 15:23:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add PsysPmax setting to 145W
by 9elements QA (Code Review) 07 Oct '21

07 Oct '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58104 ) Change subject: mb/google/brya: Add PsysPmax setting to 145W ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 7 / 1 / 8 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/80823 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/80822 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/80821 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/80820 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/80819 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/80818 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/80817 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/80816 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/58104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd Gerrit-Change-Number: 58104 Gerrit-PatchSet: 3 Gerrit-Owner: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Oct 2021 15:20:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add PsysPmax setting to 145W
by Tim Wawrzynczak (Code Review) 07 Oct '21

07 Oct '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58104 ) Change subject: mb/google/brya: Add PsysPmax setting to 145W ...................................................................... mb/google/brya: Add PsysPmax setting to 145W This patch adds the setting of PsysPmax to 145W according to the brya board design. BUG=b:195615830 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd Signed-off-by: Ryan Lin <ryan.lin(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58104 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 41d1018..ad2399b 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -32,6 +32,8 @@ chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" + register "PsysPmax" = "145" + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd Gerrit-Change-Number: 58104 Gerrit-PatchSet: 3 Gerrit-Owner: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
by Michael Niewöhner (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Felix Held. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57886 ) Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table ...................................................................... Patch Set 6: (1 comment) File src/include/acpi/acpigen.h: https://review.coreboot.org/c/coreboot/+/57886/comment/ddeda8f1_1c331df7 PS6, Line 279: _reg > But so far, we only need MSR, right? […] right, atm we only need the MSR type. oh, and the static type. yeah, I already thought about doing that. we'd need another macro for each type. not sure if I really like it, but it's better than that macro chaining. -- To view, visit https://review.coreboot.org/c/coreboot/+/57886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06 Gerrit-Change-Number: 57886 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt Delco <delco(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 07 Oct 2021 14:49:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl: Remove unneeded 'half_populated' variable
by Werner Zeh (Code Review) 07 Oct '21

07 Oct '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58177 ) Change subject: mb/siemens/mc_ehl: Remove unneeded 'half_populated' variable ...................................................................... mb/siemens/mc_ehl: Remove unneeded 'half_populated' variable Since the DRAM population is fixed to both channels on all mc_ehl boards there is no need to have this 'half_populated' variable at all. Simply use a fixed 'false' in the call of 'memcfg_init()' and delete this variable here. Change-Id: I783c17e6d92322a8b0c094cce803108e718011fa Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/58177/1 diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index a6ed234..f93e0af 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -17,9 +17,6 @@ static uint8_t spd_data[0x100]; const char *cbfs_hwi_name = "hwinfo.hex"; - /* TODO: Read the resistor strap to get number of memory segments */ - bool half_populated = false; - /* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to spd.bin in the case where the SPD data in HW-Info is not available or invalid. */ memset(spd_data, 0, sizeof(spd_data)); @@ -35,5 +32,5 @@ spd_info.spd_spec.spd_index = 0x00; } /* Initialize variant specific configurations */ - memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); + memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, false); } -- To view, visit https://review.coreboot.org/c/coreboot/+/58177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I783c17e6d92322a8b0c094cce803108e718011fa Gerrit-Change-Number: 58177 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/siemens/mc_ehl: Use SPD data from HW-Info in the first place
by Werner Zeh (Code Review) 07 Oct '21

07 Oct '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58176 ) Change subject: mb/siemens/mc_ehl: Use SPD data from HW-Info in the first place ...................................................................... mb/siemens/mc_ehl: Use SPD data from HW-Info in the first place The preferred location for the SPD data on mc_ehl based boards is the HW-Info data structure. Inside this structure there is a field of 128 bytes available for the SPD data. So in order to use it construct a buffer in memory which is 256 bytes long (as FSP requests minimum 256 bytes for the SPD data) and where the upper 128 bytes are taken from HW-Info holding the needed timing parameters for LPDDR4. If there is a case where HW-Info is not accessible or where the contained SPD data is not valid (by checking the CRC in HW-Info SPD) fall back to fixed SPD data set in CBFS. Change-Id: I2b6a1bde0306ba84f5214b876eaf76ca12d8f058 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c 1 file changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/58176/1 diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index 259870a..a6ed234 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -1,20 +1,39 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/mmio.h> #include <baseboard/variants.h> +#include <console/console.h> +#include <device/dram/common.h> +#include <hwilib.h> #include <soc/meminit.h> #include <soc/romstage.h> +#include <string.h> +#include <types.h> void mainboard_memory_init_params(FSPM_UPD *memupd) { static struct spd_info spd_info; const struct mb_cfg *board_cfg = variant_memcfg_config(); + static uint8_t spd_data[0x100]; + const char *cbfs_hwi_name = "hwinfo.hex"; /* TODO: Read the resistor strap to get number of memory segments */ bool half_populated = false; - /* Initialize spd information for LPDDR4x board */ - spd_info.read_type = READ_SPD_CBFS; - spd_info.spd_spec.spd_index = 0x00; + /* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to + spd.bin in the case where the SPD data in HW-Info is not available or invalid. */ + memset(spd_data, 0, sizeof(spd_data)); + if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) && + (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) && + (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) { + spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data; + spd_info.spd_spec.spd_data_ptr_info.spd_data_len = sizeof(spd_data); + spd_info.read_type = READ_SPD_MEMPTR; + } else { + printk(BIOS_WARNING, "SPD in HW-Info not valid, fall back to spd.bin!\n"); + spd_info.read_type = READ_SPD_CBFS; + spd_info.spd_spec.spd_index = 0x00; + } /* Initialize variant specific configurations */ memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); } -- To view, visit https://review.coreboot.org/c/coreboot/+/58176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b6a1bde0306ba84f5214b876eaf76ca12d8f058 Gerrit-Change-Number: 58176 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86,cpu/x86: Introduce new method for accessing cpu_info
by Nico Huber (Code Review) 07 Oct '21

07 Oct '21

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57627 ) Change subject: arch/x86,cpu/x86: Introduce new method for accessing cpu_info ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57627/comment/651a0eba_4d31054c PS6, Line 19: This means that when smm_do_relocation is executed, it is running in SMM > COOP_MULTITASKING doesn't change SMM code. It's only compiled into romstage/ramstage right now. […] That's why I said "code compiled into SMM relocation". I don't care if it's "ramstage code" in our build system. I'm still not sure if I fully understand what is going on. This combination of SMM relocation with code that calls cpu_info() is a new corner case, right? To me it seems like that's an issue of the caller and not of cpu_info(). Yet, your commit message states the opposite. IMO, we have to be very careful about commit messages that state too bluntly that something is broken. It will likely confuse people when they read the history later. Please don't merge commits when the commit message is not clear yet. IMHO, review can't even start before it is (unless the changes don't need any explanation of course). If the background is not fully understood, reviewers can't suggest alternatives, for instance. -- To view, visit https://review.coreboot.org/c/coreboot/+/57627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79dce9597cb784acb39a96897fb3c2f2973bfd98 Gerrit-Change-Number: 57627 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Oct 2021 14:36:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: cbgfx: Clear screen by memcpy
by Hung-Te Lin (Code Review) 07 Oct '21

07 Oct '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58128 ) Change subject: libpayload: cbgfx: Clear screen by memcpy ...................................................................... libpayload: cbgfx: Clear screen by memcpy Instead of setting each pixel in the framebuffer, use memcpy() to clear screen faster. As this method should be fast enough, remove the fast path using memset(). The speed of clear_screen() on brya (x_resolution = 1920, bytes_per_line = 7680): - Using memset(): 15ms - Setting each pixel: 25ms - Using memcpy(): 14ms Also remove set_pixel_raw() since it's now used in only one place. BUG=none TEST=emerge-brya libpayload TEST=Saw developer screen on brya BRANCH=none Change-Id: I5f08fb50faab48d3db6b61ae022af3226914f72b Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58128 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M payloads/libpayload/drivers/video/graphics.c 1 file changed, 18 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Julius Werner: Looks good to me, approved Hung-Te Lin: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 53de302..7f08d40 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -274,19 +274,12 @@ * Plot a pixel in a framebuffer. This is called from tight loops. Keep it slim * and do the validation at callers' site. */ -static inline void set_pixel_raw(struct vector *rcoord, uint32_t color) +static inline void set_pixel(struct vector *coord, uint32_t color) { const int bpp = fbinfo->bits_per_pixel; const int bpl = fbinfo->bytes_per_line; - int i; - uint8_t * const pixel = FB + rcoord->y * bpl + rcoord->x * bpp / 8; - for (i = 0; i < bpp / 8; i++) - pixel[i] = (color >> (i * 8)); -} - -static inline void set_pixel(struct vector *coord, uint32_t color) -{ struct vector rcoord; + int i; switch (fbinfo->orientation) { case CB_FB_ORIENTATION_NORMAL: @@ -308,7 +301,9 @@ break; } - set_pixel_raw(&rcoord, color); + uint8_t * const pixel = FB + rcoord.y * bpl + rcoord.x * bpp / 8; + for (i = 0; i < bpp / 8; i++) + pixel[i] = (color >> (i * 8)); } /* @@ -625,22 +620,25 @@ if (cbgfx_init()) return CBGFX_ERROR_INIT; - struct vector p; + int x, y, i; uint32_t color = calculate_color(rgb, 0); const int bpp = fbinfo->bits_per_pixel; const int bpl = fbinfo->bytes_per_line; + uint8_t *line = malloc(bpl); - /* If all significant bytes in color are equal, fastpath through memset. - * We assume that for 32bpp the high byte gets ignored anyway. */ - if ((((color >> 8) & 0xff) == (color & 0xff)) && (bpp == 16 || - (((color >> 16) & 0xff) == (color & 0xff)))) { - memset(FB, color & 0xff, fbinfo->y_resolution * bpl); - } else { - for (p.y = 0; p.y < fbinfo->y_resolution; p.y++) - for (p.x = 0; p.x < fbinfo->x_resolution; p.x++) - set_pixel_raw(&p, color); + if (!line) { + LOG("Failed to allocate line buffer (%u bytes)\n", bpl); + return CBGFX_ERROR_UNKNOWN; } + /* Set line buffer pixels, then memcpy to framebuffer */ + for (x = 0; x < fbinfo->x_resolution; x++) + for (i = 0; i < bpp / 8; i++) + line[x * bpp / 8 + i] = (color >> (i * 8)); + for (y = 0; y < fbinfo->y_resolution; y++) + memcpy(FB + y * bpl, line, bpl); + + free(line); return CBGFX_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/58128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f08fb50faab48d3db6b61ae022af3226914f72b Gerrit-Change-Number: 58128 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: libpayload: cbgfx: Clear screen by memcpy
by Hung-Te Lin (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58128 ) Change subject: libpayload: cbgfx: Clear screen by memcpy ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f08fb50faab48d3db6b61ae022af3226914f72b Gerrit-Change-Number: 58128 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 07 Oct 2021 14:11:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: [WIP]Trigger cse_fw_sync before DRAM Init
by build bot (Jenkins) (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Sridhar Siricilla, Tim Wawrzynczak, Ravindra, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55364 ) Change subject: soc/intel/alderlake: [WIP]Trigger cse_fw_sync before DRAM Init ...................................................................... Patch Set 6: Verified+1 (1 comment) File src/soc/intel/alderlake/romstage/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129975): https://review.coreboot.org/c/coreboot/+/55364/comment/814ed456_18e1da55 PS6, Line 140: if (!s3wake) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/55364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Gerrit-Change-Number: 55364 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 07 Oct 2021 14:08:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2021