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Change subject: drivers/intel/dptf: Add support for PCH methods
......................................................................
Patch Set 8:
(2 comments)
File src/drivers/intel/dptf/dptf.c:
https://review.coreboot.org/c/coreboot/+/57925/comment/66158dcd_10dfe268
PS7, Line 230: acpigen_write_package(1);
: acpigen_write_zero();
> Since this is unrelated to this change, could this be separate commit? Also please update the commen […]
Submitted separate CL for this https://review.coreboot.org/c/coreboot/+/58174https://review.coreboot.org/c/coreboot/+/57925/comment/8781d0f4_a93f8f12
PS7, Line 292: "\\_SB_.DPTF.TPCH.PKGC"
> I think just […]
Done
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Change subject: drivers/intel/dptf: return package with value
......................................................................
drivers/intel/dptf: return package with value
Return the package with a value for the dptf user space service.
This is required in write tpch method for pch device under dptf
driver.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I64e1bb04a6115c7f93c84a5d6644101ac1d3d8ba
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/drivers/intel/dptf/dptf.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/58174/1
diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c
index 4a65127..c6ead0f 100644
--- a/src/drivers/intel/dptf/dptf.c
+++ b/src/drivers/intel/dptf/dptf.c
@@ -227,7 +227,8 @@
acpigen_write_zero();
/* The reason for returning a value here is a W/A for the ESIF shell */
acpigen_emit_byte(RETURN_OP);
- acpigen_write_package(0);
+ acpigen_write_package(1);
+ acpigen_write_zero();
acpigen_write_package_end();
acpigen_write_method_end();
}
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I'd like you to reexamine a change. Please visit
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Change subject: drivers/intel/dptf: Add support for PCH methods
......................................................................
drivers/intel/dptf: Add support for PCH methods
Add various methods support for pch device under dptf driver.
This provides support of different control knobs for FIVR.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/drivers/intel/dptf/dptf.c
M src/drivers/intel/dptf/dptf.h
M src/soc/intel/alderlake/dptf.c
3 files changed, 162 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/57925/8
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Change subject: soc/intel/alderlake: [WIP]Trigger cse_fw_sync before DRAM Init
......................................................................
Patch Set 5: Verified+1
(1 comment)
File src/soc/intel/alderlake/romstage/romstage.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129970):
https://review.coreboot.org/c/coreboot/+/55364/comment/b8f89048_a4b63b6b
PS5, Line 140: if (!s3wake) {
braces {} are not necessary for single statement blocks
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: [WIP]Trigger cse_fw_sync before DRAM Init
......................................................................
soc/intel/alderlake: [WIP]Trigger cse_fw_sync before DRAM Init
The patch enables cse_fw_sync() before DRAM Init.
TEST=Dependency with CSE Lite SKU
Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com>
---
M src/soc/intel/alderlake/romstage/romstage.c
1 file changed, 8 insertions(+), 7 deletions(-)
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Change subject: soc/intel/common: Add HECI Reset flow in the CSE driver
......................................................................
soc/intel/common: Add HECI Reset flow in the CSE driver
The patch adds HECI Reset flow in the CSE driver. This is required as part
of the HECI Interface initialization in order to put the host and CSE into
a known good state for communication. This change is required to send
HECI commands before DRAM Init.
TEST=Run 50 cold reset cycles on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba
---
M src/soc/intel/common/block/cse/cse.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55363/6
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57886 )
Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
......................................................................
Patch Set 6:
(1 comment)
File src/include/acpi/acpigen.h:
https://review.coreboot.org/c/coreboot/+/57886/comment/7b9a2a37_573ad35d
PS6, Line 279: _reg
> I agree with checkpatch about the spaces. Maybe to avoid the nesting, […]
The reason for doing that is that `CPPC_REG` is generic but not MSR-only. It could be *any* register resource type (memory, io, msr)
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Change subject: soc/intel/alderlake: [WIP]Trigger cse_fw_sync before DRAM Init
......................................................................
Patch Set 4: Verified+1
(1 comment)
File src/soc/intel/alderlake/romstage/romstage.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129968):
https://review.coreboot.org/c/coreboot/+/55364/comment/a9e2c378_f066961e
PS4, Line 140: if (!s3wake) {
braces {} are not necessary for single statement blocks
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Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58172 )
Change subject: mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devices
......................................................................
mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devices
On this mainboard there is a legacy PCI device, which is connected to
the PCIe root port via a PCIe-2-PCI bridge. This device only supports
legacy interrupt routing. For this reason, we have to adjust the PIR8
register (0x3150) which is responsible for PCIe device 25h. The bridge
is connected to PCIe root port 7.
The following routing is required:
INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB#
Change-Id: Id6bb8d00458c4d1e3fefd01ac3848078355868d9
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc
A src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c
2 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/58172/1
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc
index 9cb0f1d..2903dd1 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc
@@ -3,6 +3,7 @@
bootblock-y += gpio.c
romstage-y += memory.c
ramstage-y += gpio.c
+ramstage-y += mainboard.c
SPD_SOURCES = mc_ehl2 # 0b000
LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), \
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c
new file mode 100644
index 0000000..a58a79e
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+
+void variant_mainboard_final(void)
+{
+ /* PIR8 register mapping for PCIe root ports
+ * INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB#
+ */
+ pcr_write16(PID_ITSS, 0x3150, 0x1032);
+ printk(BIOS_INFO, "PIRQ routing adapted for SOC2\n");
+}
--
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