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Change subject: mb/siemens/mc_ehl2: Update SPD for DDR4 devices
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58111/comment/ba3b1564_38ba9df7
PS3, Line 9: devices
> Are these the memory chips (“modules”). […]
I have added it.
https://review.coreboot.org/c/coreboot/+/58111/comment/cbe8d445_d2da739a
PS3, Line 11:
> As you are editing a hex file, what values/options are you changing? Where did you get these from? […]
Following values were adjusted according to this board characteristic and with help of Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules JEDEC Spec and the Specification for this Micron modules itself:
SPD Byte 4 – only 4Gb density instead of 8Gb for mc_ehl1
SPD Byte 5 – different Row and Column Address Bits
SPD Byte 29/30 – 4Gb LPDDR4 needs 130ns tRFCab
SPD Byte 31/32 – 4Gb LPDDR4 needs 60ns tRFCpb
...and yes, with the mc_ehl1 settings the board didn’t boot.
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Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58111
to look at the new patch set (#4).
Change subject: mb/siemens/mc_ehl2: Update SPD for DDR4 devices
......................................................................
mb/siemens/mc_ehl2: Update SPD for DDR4 devices
Since this variant uses different DDR4 devices compared to mc_ehl1 in a
memory down configuration, the SPD data file must be adapted.
In a first configuration we use Micron MT53D512M32D2NP modules.
Change-Id: Icb25f418952f0c96117140863d0d9c897d814ac5
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/spd/mc_ehl2.spd.hex
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/58111/4
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57886 )
Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
......................................................................
Patch Set 6:
(1 comment)
File src/include/acpi/acpigen.h:
https://review.coreboot.org/c/coreboot/+/57886/comment/7c7f4c43_00340ec6
PS6, Line 279: _reg
> The reason for doing that is that `CPPC_REG` is generic but not MSR-only. […]
But so far, we only need MSR, right?
Don't want to fight about it... how about
#define CPPC_MSR(addr, offset, width) CPPC_REG(ACPI_REG_MSR(addr, offset, width))
?
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Change subject: mb/system76: tgl-u: Add gfx register for GMA ACPI
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/system76/darp7/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/57835/comment/7233acd8_5a44578b
PS1, Line 110: GMA_STATIC_DISPLAYS
> This is a short form for some legacy copy-pasta that we couldn't remove […]
Done
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Hello build bot (Jenkins),
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Change subject: mb/system76: tgl-u: Add gfx register for GMA ACPI
......................................................................
mb/system76: tgl-u: Add gfx register for GMA ACPI
Add gfx register to System76 TGL-U boards so GMA ACPI data is generated.
Change-Id: If944a90921b518efdcd5f0e0998bddb4f56e5764
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---
M src/mainboard/system76/darp7/devicetree.cb
M src/mainboard/system76/galp5/devicetree.cb
M src/mainboard/system76/lemp10/devicetree.cb
3 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/57835/2
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Change subject: mb/ocp/deltalake: Fix SMBIOS type 9 bugs
......................................................................
Patch Set 8: Code-Review+1
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Change subject: mb/google/brya/variants/brask: Init the overridetree
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58165/comment/470a4d4a_ce59dda3
PS1, Line 7: Init the overridetree
Init overridetree
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