coreboot-gerrit October 2021

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Change in coreboot[master]: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
by Michael Niewöhner (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Felix Singer, Lance Zhao, Jason Glenesk, Raul Rangel, Nico Huber, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, Felix Held. Hello Felix Singer, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Patrick Rudolph, Lance Zhao, Jason Glenesk, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Tim Wawrzynczak, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58118 to look at the new patch set (#4). Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing ...................................................................... acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing Instead of passing around a magic struct with embedded version, use pointers and pass the CPPC version directly to the ACPI generator. Change-Id: I26c5e80c2a16a50ed73245c7c32d61b17e45c22a Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/acpi/acpigen.c M src/cpu/intel/common/common.h M src/cpu/intel/common/common_init.c M src/include/acpi/acpi.h M src/include/acpi/acpigen.h M src/soc/amd/cezanne/cppc.c M src/soc/amd/cezanne/include/soc/cppc.h M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/skylake/acpi.c 9 files changed, 99 insertions(+), 108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/58118/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26c5e80c2a16a50ed73245c7c32d61b17e45c22a Gerrit-Change-Number: 58118 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
by Michael Niewöhner (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Felix Held. Hello Felix Singer, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Lance Zhao, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Tim Wawrzynczak, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57886 to look at the new patch set (#7). Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table ...................................................................... acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table Some elements in the ACPI CPPC table allow static DWORDs. Instead of using a fake register resource, use a tagged union with the two types "register" and "DWORD" and respective macros for CPPC table entries. Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/acpi/acpigen.c M src/cpu/intel/common/common.h M src/cpu/intel/common/common_init.c M src/include/acpi/acpigen.h M src/soc/amd/cezanne/cppc.c M src/soc/amd/cezanne/include/soc/cppc.h 6 files changed, 73 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/57886/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/57886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06 Gerrit-Change-Number: 57886 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt Delco <delco(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/cse_serger: Add a new tool for stitching CSE components
by build bot (Jenkins) (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Cliff Huang, Furquan Shaikh, Martin Roth, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Bernardo Perez Priego, Andrew McRae. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55503 ) Change subject: util/cse_serger: Add a new tool for stitching CSE components ...................................................................... Patch Set 19: Verified-1 (3 comments) File util/cbfstool/bpdt_formats/subpart_entry_1.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129995): https://review.coreboot.org/c/coreboot/+/55503/comment/4ec1f1ca_49a66b00 PS19, Line 49: printf("%-25s%-25s%-25s%-25s%-25s%-25s\n", "Entry #", "Name", "Offset", "Huffman Compressed?", line over 96 characters File util/cbfstool/cse_serger.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129995): https://review.coreboot.org/c/coreboot/+/55503/comment/aa4357db_1098d9aa PS19, Line 272: ERROR("Part(%d) exceeds file size. Part offset=0x%x, Part size = 0x%x, File size = 0x%zx\n", line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129995): https://review.coreboot.org/c/coreboot/+/55503/comment/99222b55_97ec13b7 PS19, Line 923: if (c < LONGOPT_START) { braces {} are not necessary for any arm of this statement -- To view, visit https://review.coreboot.org/c/coreboot/+/55503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90dd809b47fd16afdc80e66431312721082496aa Gerrit-Change-Number: 55503 Gerrit-PatchSet: 19 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.corp-partner.google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.corp-partner.google.com> Gerrit-Attention: Andrew McRae <amcrae(a)google.com> Gerrit-Comment-Date: Thu, 07 Oct 2021 18:23:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Update GPP_D5 configuration
by Karthik Ramasubramanian (Code Review) 07 Oct '21

07 Oct '21

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58073 ) Change subject: mb/google/dedede/var/bugzzy: Update GPP_D5 configuration ...................................................................... mb/google/dedede/var/bugzzy: Update GPP_D5 configuration As we checked the panel doesn't display firmware screen if we hold GPP_D5(TOUCHSCREEN_RESET) low on bugzzy. It's because of that bugzzy uses the built-in touch screen on the panel, the panel seems like under reset state by the TOUCHSCREEN_RESET signal. This change sets default GPP_D5 level to high for bugzzy. BUG=b:None BRANCH=dedede TEST=built and verified bugzzy showed firmware screen Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58073 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward Doan <edoan(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/bugzzy/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Edward Doan: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/bugzzy/gpio.c b/src/mainboard/google/dedede/variants/bugzzy/gpio.c index ce88b5e..d089162 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/gpio.c +++ b/src/mainboard/google/dedede/variants/bugzzy/gpio.c @@ -21,6 +21,8 @@ PAD_NC(GPP_D1, NONE), /* D3 : WLAN_PCIE_WAKE_ODL ==> NC */ PAD_NC(GPP_D3, NONE), + /* D5 : TOUCHSCREEN_RESET */ + PAD_CFG_GPO(GPP_D5, 1, DEEP), /* D7 : EMR_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D7, NONE, PLTRST, LEVEL, INVERT), /* D13 : EN_PP3300_CAMERA */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1 Gerrit-Change-Number: 58073 Gerrit-PatchSet: 2 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Edward Doan <edoan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Clear SLP_S0_GATE_L on S5 shutdown
by Furquan Shaikh (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58180 ) Change subject: mb/google/brya: Clear SLP_S0_GATE_L on S5 shutdown ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/brya/mainboard.asl: https://review.coreboot.org/c/coreboot/+/58180/comment/0b0d5fe0_843833c8 PS1, Line 30: S5 shutdown This is not just S5 shutdown but any sleep entry, right? Also, how does this work in case of S0ix? Is _PTS called in that case too? https://review.coreboot.org/c/coreboot/+/58180/comment/34570004_297da4a2 PS1, Line 33: */ Add comment that this gets reconfigured correctly on wake from sleep path i.e. in ramstage. -- To view, visit https://review.coreboot.org/c/coreboot/+/58180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5500e701ac8731d141b51dc381609c80047dc1f8 Gerrit-Change-Number: 58180 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 07 Oct 2021 18:19:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Clear SLP_S0_GATE_L on S5 shutdown
by Tim Wawrzynczak (Code Review) 07 Oct '21

07 Oct '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58180 ) Change subject: mb/google/brya: Clear SLP_S0_GATE_L on S5 shutdown ...................................................................... mb/google/brya: Clear SLP_S0_GATE_L on S5 shutdown On brya platforms, the SLP_S0_L signal is gated to the rest of the platform by SLP_S0_GATE_L, which is under software control. Currently, this GPIO is not touched on the powerdown sequence, leading to the rest of the platform observing the SLP_S0_L signal deassert far too late, and thus the EC gets confused. Currently, the EC power state machine observes the following transitions during powerdown: S0->S3->S5->G3->S3->S5->G3 With this patch: S0->S3->S5->G3 BUG=b:186707518 TEST=observe power state transitions in EC console as described above Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I5500e701ac8731d141b51dc381609c80047dc1f8 --- M src/mainboard/google/brya/mainboard.asl M src/mainboard/google/brya/wwan_power.asl 2 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/58180/1 diff --git a/src/mainboard/google/brya/mainboard.asl b/src/mainboard/google/brya/mainboard.asl index c60db30..330bcc3 100644 --- a/src/mainboard/google/brya/mainboard.asl +++ b/src/mainboard/google/brya/mainboard.asl @@ -22,3 +22,18 @@ \_SB.PCI0.STXS(GPIO_SLP_S0_GATE); } } + +/* Mainboard _PTS override */ +Method (MPTS, 1) +{ + /* + * On S5 shutdown, clear the SLP_S0_GATE pin, so that the rest of the + * platform can observe SLP_S0_L transition at the correct point in + * the shutdown sequence. + */ + \_SB.PCI0.CTXS(GPIO_SLP_S0_GATE); + +#if CONFIG(HAVE_WWAN_POWER_SEQUENCE) + WWPD() +#endif +} diff --git a/src/mainboard/google/brya/wwan_power.asl b/src/mainboard/google/brya/wwan_power.asl index d9bb5e7..4f33152 100644 --- a/src/mainboard/google/brya/wwan_power.asl +++ b/src/mainboard/google/brya/wwan_power.asl @@ -2,7 +2,7 @@ #include <variant/gpio.h> -Method (MPTS, 1) +Method (WWPD, 0) { \_SB.PCI0.CTXS(WWAN_PERST); Sleep(T1_OFF_MS) -- To view, visit https://review.coreboot.org/c/coreboot/+/58180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5500e701ac8731d141b51dc381609c80047dc1f8 Gerrit-Change-Number: 58180 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: TESTONLY: mb/google/brya: Enable CSE stitching
by Furquan Shaikh (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Cliff Huang, Tim Wawrzynczak, Bernardo Perez Priego. Hello build bot (Jenkins), Cliff Huang, Tim Wawrzynczak, Bernardo Perez Priego, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58127 to look at the new patch set (#9). Change subject: TESTONLY: mb/google/brya: Enable CSE stitching ...................................................................... TESTONLY: mb/google/brya: Enable CSE stitching Change-Id: Ib4e74a499d1e02003a5de32102ef58456a0990c5 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/58127/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/58127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4e74a499d1e02003a5de32102ef58456a0990c5 Gerrit-Change-Number: 58127 Gerrit-PatchSet: 9 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Add sub-regions to SI_ME in chromeos.fmd
by Furquan Shaikh (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Cliff Huang, Tim Wawrzynczak, Bernardo Perez Priego. Hello build bot (Jenkins), Cliff Huang, Tim Wawrzynczak, Bernardo Perez Priego, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58126 to look at the new patch set (#9). Change subject: mb/google/brya: Add sub-regions to SI_ME in chromeos.fmd ...................................................................... mb/google/brya: Add sub-regions to SI_ME in chromeos.fmd This change adds sub-regions to SI_ME in chromeos.fmd. These are required to support stitching of CSE components. Change-Id: I4da677da2e24b0398d04786e71490611db635ead Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/brya/chromeos.fmd 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/58126/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/58126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4da677da2e24b0398d04786e71490611db635ead Gerrit-Change-Number: 58126 Gerrit-PatchSet: 9 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Enable support for CSE stitching
by Furquan Shaikh (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Cliff Huang, Tim Wawrzynczak, Bernardo Perez Priego, Patrick Rudolph. Hello build bot (Jenkins), Cliff Huang, Tim Wawrzynczak, Bernardo Perez Priego, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58125 to look at the new patch set (#9). Change subject: soc/intel/alderlake: Enable support for CSE stitching ...................................................................... soc/intel/alderlake: Enable support for CSE stitching Change-Id: I2b14405aab2a4919431d9c16bc7ff2eb1abf1f6b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc 2 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/58125/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/58125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b14405aab2a4919431d9c16bc7ff2eb1abf1f6b Gerrit-Change-Number: 58125 Gerrit-PatchSet: 9 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Makefile: Add src/soc/* to subdirs
by Furquan Shaikh (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Cliff Huang, Martin Roth, Tim Wawrzynczak, Bernardo Perez Priego. Hello build bot (Jenkins), Cliff Huang, Martin Roth, Patrick Georgi, Tim Wawrzynczak, Bernardo Perez Priego, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58124 to look at the new patch set (#8). Change subject: Makefile: Add src/soc/* to subdirs ...................................................................... Makefile: Add src/soc/* to subdirs This change adds src/soc/* to subdirs before src/soc/*/* to allow Makefile in src/soc/* to provide any common helpers that will be useful for any src/soc/*/*. This is done to primarily ensure that the helpers are defined before being invoked by the SoC Makefile.inc. This is utilized by Intel CSE stitching mechanism in following changes. Change-Id: I91579a87016fdc2b9ca2d798b81969c21c18b4a3 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/58124/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/58124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91579a87016fdc2b9ca2d798b81969c21c18b4a3 Gerrit-Change-Number: 58124 Gerrit-PatchSet: 8 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2021