Attention is currently required from: John Zhao, Paul Menzel.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57625 )
Change subject: soc/intel/tigerlake: Add ACPI addition for USB4/TBT latency optimization
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
File src/soc/intel/tigerlake/acpi/tcss_pcierp.asl:
https://review.coreboot.org/c/coreboot/+/57625/comment/2b948fd8_44a6dfd0
PS3, Line 114: FUN9 = 1
Technically shouldn't bit 0 be set as well?
--
To view, visit https://review.coreboot.org/c/coreboot/+/57625
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5a19118b75ed0a78b7436f2f90295c03928300d7
Gerrit-Change-Number: 57625
Gerrit-PatchSet: 3
Gerrit-Owner: John Zhao <john.zhao(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: John Zhao <john.zhao(a)intel.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Comment-Date: Thu, 07 Oct 2021 22:06:06 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
Attention is currently required from: Ravi kumar.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58144 )
Change subject: sc7180: Update video mode active horizontal/vertical/total calculations
......................................................................
Patch Set 1: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/58144
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9ccafabe226fa53c6f82e32413d4c00a0b4531be
Gerrit-Change-Number: 58144
Gerrit-PatchSet: 1
Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com>
Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org>
Gerrit-Comment-Date: Thu, 07 Oct 2021 21:19:47 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
Attention is currently required from: Anil Kumar K.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58153
to look at the new patch set (#4).
Change subject: [Test] mb/adlrvp: hard code sku id to 2147483647 and update part number
......................................................................
[Test] mb/adlrvp: hard code sku id to 2147483647 and update part number
Change-Id: Id168133406e8033995d80b13cca21b79d5aa21d6
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/mainboard.c
2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/58153/4
--
To view, visit https://review.coreboot.org/c/coreboot/+/58153
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id168133406e8033995d80b13cca21b79d5aa21d6
Gerrit-Change-Number: 58153
Gerrit-PatchSet: 4
Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-MessageType: newpatchset
Attention is currently required from: Anil Kumar K.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58153
to look at the new patch set (#3).
Change subject: Test: adlrvp: hard code sku id to 2147483647
......................................................................
Test: adlrvp: hard code sku id to 2147483647
Change-Id: Id168133406e8033995d80b13cca21b79d5aa21d6
---
M src/mainboard/intel/adlrvp/mainboard.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/58153/3
--
To view, visit https://review.coreboot.org/c/coreboot/+/58153
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id168133406e8033995d80b13cca21b79d5aa21d6
Gerrit-Change-Number: 58153
Gerrit-PatchSet: 3
Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-MessageType: newpatchset
Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58181 )
Change subject: soc/intel/common/cse: Support RW update when stitching CSE binary
......................................................................
soc/intel/common/cse: Support RW update when stitching CSE binary
This change updates the STITCH_ME_BIN path to enable support for
including CSE RW update in CBFS. CSE_RW_FILE is set to either
CONFIG_SOC_INTEL_CSE_RW_FILE or CSE_BP2_BIN depending upon the
selection of STITCH_ME_BIN config. Also, $(CSE_LITE_ME_RW)-file is
updated to be evaluated every time it is used so that there is no
dependency on the order of definitions in Makefile.inc.
Change-Id: I0478f6b2a3342ed29c7ca21aa8e26655c58265f4
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
2 files changed, 11 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/58181/1
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index 247cc9f..5b3ad0b 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -64,7 +64,7 @@
CBFS name for Intel CSE CBFS RW version file
config SOC_INTEL_CSE_RW_FILE
- string "Intel CSE CBFS RW path and filename" if SOC_INTEL_CSE_RW_UPDATE
+ string "Intel CSE CBFS RW path and filename" if SOC_INTEL_CSE_RW_UPDATE && !STITCH_ME_BIN
default ""
help
Intel CSE CBFS RW blob path and file name
diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc
index fc54b82..4139b48 100644
--- a/src/soc/intel/common/block/cse/Makefile.inc
+++ b/src/soc/intel/common/block/cse/Makefile.inc
@@ -8,21 +8,24 @@
ifeq ($(CONFIG_SOC_INTEL_CSE_RW_UPDATE),y)
-ifeq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"")
-$(error "CSE RW file path is missing and need to be set by mainboard config")
-endif
-
ifeq ($(CONFIG_SOC_INTEL_CSE_RW_VERSION),"")
$(error "CSE RW version is missing and need to be set by mainboard config")
endif
-CSE_RW_FILE=$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE))
+ifneq ($(CONFIG_STITCH_ME_BIN),y)
+
+ifeq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"")
+$(error "CSE RW file path is missing and need to be set by mainboard config")
+endif
+CSE_RW_FILE := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE))
+
+endif
CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME))
regions-for-file-$(CSE_LITE_ME_RW) = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_A_FMAP_NAME)), \
$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_B_FMAP_NAME))
cbfs-files-y += $(CSE_LITE_ME_RW)
-$(CSE_LITE_ME_RW)-file := $(CSE_RW_FILE)
+$(CSE_LITE_ME_RW)-file = $(CSE_RW_FILE)
$(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW)
$(CSE_LITE_ME_RW)-type := raw
@@ -53,6 +56,7 @@
CSE_BP1_BIN := $(objcse)/cse_bp1.bin
CSE_BP2_BIN := $(objcse)/cse_bp2.bin
CSE_LAYOUT_BIN := $(objcse)/cse_layout.bin
+CSE_RW_FILE := $(CSE_BP2_BIN)
CSE_BPDT_VERSION := $(call strip_quotes,$(CONFIG_CSE_BPDT_VERSION))
ifeq ($(CONFIG_CSE_BPDT_VERSION),)
--
To view, visit https://review.coreboot.org/c/coreboot/+/58181
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0478f6b2a3342ed29c7ca21aa8e26655c58265f4
Gerrit-Change-Number: 58181
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Gerrit-MessageType: newchange
Attention is currently required from: Jakub Czapiga, Julius Werner, Jan Dabros, Yu-Ping Wu.
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58163 )
Change subject: tests: Fix JUNIT_OUTPUT=y to write to files instead of stderr
......................................................................
Patch Set 2: Code-Review+2
(2 comments)
File tests/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/58163/comment/2c8be5a0_65c5108c
PS2, Line 232: rm -f $(testobj)/junit-$(subst /,_,$(patsubst $(testobj)/%/,%,$(dir $^)))\(*\).xml
> It could work, but $^ here refers to $$($$(@)-bin). […]
so many nested parens ....
you're right. Leave it this way.
https://review.coreboot.org/c/coreboot/+/58163/comment/27484df9_1d184cfb
PS2, Line 233: rm -f $(testobj)/$(subst /,_,$^).failed
> Same as above.
Ack
--
To view, visit https://review.coreboot.org/c/coreboot/+/58163
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I09891aca923bf1271cafeaa09f89b6539022709c
Gerrit-Change-Number: 58163
Gerrit-PatchSet: 2
Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com>
Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com>
Gerrit-Attention: Julius Werner <jwerner(a)chromium.org>
Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com>
Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Comment-Date: Thu, 07 Oct 2021 19:31:23 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com>
Comment-In-Reply-To: Paul Fagerburg <pfagerburg(a)chromium.org>
Gerrit-MessageType: comment
Attention is currently required from: David Wu, Alan Huang.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58165 )
Change subject: mb/google/brya/variants/brask: Init the overridetree
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58165/comment/4e2eec3e_ec45b6d8
PS1, Line 9: Init the overridetree
same here
--
To view, visit https://review.coreboot.org/c/coreboot/+/58165
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I30d26a47fe93736c63b578c9180b148ef73e8b9f
Gerrit-Change-Number: 58165
Gerrit-PatchSet: 1
Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com>
Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com>
Gerrit-Comment-Date: Thu, 07 Oct 2021 19:08:41 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment