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Change subject: mb/google/brya: Clear SLP_S0_GATE_L on ACPI sleep entry
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/mainboard/google/brya/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/58180/comment/0b79693a_b807797d
PS1, Line 30: S5 shutdown
> On entry of S1-S5 yes. _PTS is not called for s2idle cases (ACPI has different s2idle vs. […]
Ack.
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Change subject: drivers/intel/dptf: return package with value
......................................................................
Patch Set 1: Code-Review+2
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Change subject: drivers/intel/dptf: Add support for PCH methods
......................................................................
Patch Set 8: Code-Review+2
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Change subject: soc/intel/alderlake: [WIP]Trigger cse_fw_sync before DRAM Init
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/alderlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/55364/comment/ceeae825_18d0a610
PS3, Line 133: if (!s3wake) {
: if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
> Nit: You could put it in one line.
e.g.
```
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake)
cse_fw_sync();
```
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Change subject: mb/google/brya: Clear SLP_S0_GATE_L on ACPI sleep entry
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/brya/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/58180/comment/3c85115e_45c0d046
PS1, Line 30: S5 shutdown
> This is not just S5 shutdown but any sleep entry, right? […]
On entry of S1-S5 yes. _PTS is not called for s2idle cases (ACPI has different s2idle vs. suspend PM ops, and the s2idle prepare callback does not end up calling _PTS. Otherwise I think there would be no need for the LPIT S0ix hooks?
Updated comment 😊
https://review.coreboot.org/c/coreboot/+/58180/comment/4568d8e2_7657a2cb
PS1, Line 33: */
> Add comment that this gets reconfigured correctly on wake from sleep path i.e. in ramstage.
Done
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58118 )
Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
......................................................................
Patch Set 4:
(14 comments)
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130003):
https://review.coreboot.org/c/coreboot/+/58118/comment/28e70479_abd1352a
PS4, Line 15: [CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130003):
https://review.coreboot.org/c/coreboot/+/58118/comment/42125261_987b15c3
PS4, Line 16: [CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130003):
https://review.coreboot.org/c/coreboot/+/58118/comment/5571279d_282dfa48
PS4, Line 17: [CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130003):
https://review.coreboot.org/c/coreboot/+/58118/comment/a3ca50a9_8db53e25
PS4, Line 18: [CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130003):
https://review.coreboot.org/c/coreboot/+/58118/comment/15eaa538_ce9b92f3
PS4, Line 20: [CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130003):
https://review.coreboot.org/c/coreboot/+/58118/comment/155ba320_7858039a
PS4, Line 21: [CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130003):
https://review.coreboot.org/c/coreboot/+/58118/comment/65af6cdf_5eadf3c3
PS4, Line 22: [CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130003):
https://review.coreboot.org/c/coreboot/+/58118/comment/42210587_4fcca501
PS4, Line 26: [CPPC_REF_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130003):
https://review.coreboot.org/c/coreboot/+/58118/comment/c2386666_2727879f
PS4, Line 26: [CPPC_REF_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64),
space prohibited after that open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130003):
https://review.coreboot.org/c/coreboot/+/58118/comment/c7452d31_3a380c05
PS4, Line 27: [CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130003):
https://review.coreboot.org/c/coreboot/+/58118/comment/cf5a2b1c_9af316fb
PS4, Line 27: [CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64),
space prohibited after that open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130003):
https://review.coreboot.org/c/coreboot/+/58118/comment/392ed1ac_517f49c9
PS4, Line 28: [CPPC_PERF_LIMITED] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_STATUS, 1, 1),
space prohibited after that open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130003):
https://review.coreboot.org/c/coreboot/+/58118/comment/002f00fb_bb799c4a
PS4, Line 29: [CPPC_ENABLE] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_ENABLE, 0, 1),
space prohibited after that open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130003):
https://review.coreboot.org/c/coreboot/+/58118/comment/e395255f_722a8c8d
PS4, Line 34: [CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8),
line over 96 characters
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Hello Furquan Shaikh, Nick Vaccaro, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58180
to look at the new patch set (#2).
Change subject: mb/google/brya: Clear SLP_S0_GATE_L on ACPI sleep entry
......................................................................
mb/google/brya: Clear SLP_S0_GATE_L on ACPI sleep entry
On brya platforms, the SLP_S0_L signal is gated to the rest of the
platform by SLP_S0_GATE_L, which is under software control. Currently,
this GPIO is not touched on the S5 shutdown path, leading to the rest of
the platform observing the SLP_S0_L signal deassert far too late, and
thus the EC gets confused.
Currently, the EC power state machine observes the following
transitions during powerdown:
S0->S3->S5->G3->S3->S5->G3
With this patch:
S0->S3->S5->G3
BUG=b:186707518
TEST=observe power state transitions in EC console as described above
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I5500e701ac8731d141b51dc381609c80047dc1f8
---
M src/mainboard/google/brya/mainboard.asl
M src/mainboard/google/brya/wwan_power.asl
2 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/58180/2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57886 )
Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
......................................................................
Patch Set 7:
(15 comments)
File src/cpu/intel/common/common_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/450ff552_4d22f2af
PS7, Line 108: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/d40d0582_a4a44328
PS7, Line 110: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/5875e304_cb2f127c
PS7, Line 111: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/b94cae2f_1636e5b1
PS7, Line 112: config->entries[CPPC_GUARANTEED_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/ea93bd71_8e8e0b63
PS7, Line 128: config->entries[CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG_MSR(IA32_HWP_REQUEST, 32, 10);
line over 96 characters
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/0d030a60_35a51e12
PS7, Line 18: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/7723062e_e9a44a25
PS7, Line 19: config->entries[CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/098ec435_025f5edc
PS7, Line 20: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/9f977fd7_cfe01fcb
PS7, Line 21: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/449d33d3_1254616a
PS7, Line 23: config->entries[CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/39da7e42_b46a46e6
PS7, Line 24: config->entries[CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/a214fd1e_9b68cc5f
PS7, Line 25: config->entries[CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/7841eb13_7a47583d
PS7, Line 29: config->entries[CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/27b009f9_086e012f
PS7, Line 30: config->entries[CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
https://review.coreboot.org/c/coreboot/+/57886/comment/7af5584e_07a8f518
PS7, Line 39: config->entries[CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
line over 96 characters
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