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Change subject: herobrine: change board ID detect to tristate solution.
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/herobrine/boardid.c:
https://review.coreboot.org/c/coreboot/+/58042/comment/f0b65382_165a3daf
PS3, Line 20: gpio_binary_first_base3_value
No, this should be gpio_base3_value per https://issuetracker.google.com/193807794
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Change subject: soc/intel/{skl,cnl,dnv,xeon_sp}: disable PM ACPI timer if chosen
......................................................................
Patch Set 33:
(1 comment)
File src/soc/intel/xeon_sp/pmc.c:
https://review.coreboot.org/c/coreboot/+/57932/comment/0e8aca40_425de11f
PS33, Line 60: Disabling ACPI PM timer also switches off TCO.
I didn't find any documentation mention disable PM timer will stop TCO, any link please?
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Change subject: soc/intel/{common,skl}: set ACPI_FADT_PLATFORM_CLOCK based on Kconfig
......................................................................
Patch Set 27:
(1 comment)
Patchset:
PS27:
> Did I miss a case? Where do you see that mismatch?
What I mean is seems current linux kernel do not have any extra action base on this flag, maybe windows is different?
The change itself is good, though I may want to know how you think of the change from beginning.
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Change subject: sc7280: Add GSI FW download support
......................................................................
Patch Set 19:
(1 comment)
File src/soc/qualcomm/sc7280/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/56590/comment/68ee09d9_22e6b194
PS19, Line 139: none
does compression work here?
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Change subject: mb/google/sarien: Add default fmap for non-ChromeOS builds
......................................................................
Patch Set 2: Code-Review+1
(2 comments)
File src/mainboard/google/sarien/default.fmd:
PS2:
nit: It seems that there are no gaps and that they all follow one another. So I would just use the region sizes (like you did with RP_VPD or FMAP).
https://review.coreboot.org/c/coreboot/+/58184/comment/9a9be1f1_13fd9b1c
PS2, Line 7: SI_PDR(PRESERVE)@0x3fc000 0x4000
What is this region for?
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Change subject: mb/google/hatch/var/scout: set correct i2c configuration
......................................................................
Set Ready For Review
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Change subject: tests: Add lib/lzma-test test case
......................................................................
Patch Set 9: Code-Review+2
(1 comment)
File tests/lib/lzma-test.c:
https://review.coreboot.org/c/coreboot/+/57555/comment/6476350d_4bb97b4f
PS8, Line 167: */
> Done. […]
Up to you... I think this is certainly fine as it is (and there are other important things to do). If you want to add more, I'd try to focus on testing different LZMA configurations (e.g. different dict size or whatever else you can play with in the filter chain arguments to the lzma util), not just more random files compressed the same way.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58177 )
Change subject: mb/siemens/mc_ehl: Remove unneeded 'half_populated' variable
......................................................................
mb/siemens/mc_ehl: Remove unneeded 'half_populated' variable
Since the DRAM population is fixed to both channels on all mc_ehl boards
there is no need to have this 'half_populated' variable at all.
Simply use a fixed 'false' in the call of 'memcfg_init()' and delete
this variable here.
Change-Id: I783c17e6d92322a8b0c094cce803108e718011fa
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58177
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---
M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
1 file changed, 1 insertion(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
index a6ed234..f93e0af 100644
--- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
+++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
@@ -17,9 +17,6 @@
static uint8_t spd_data[0x100];
const char *cbfs_hwi_name = "hwinfo.hex";
- /* TODO: Read the resistor strap to get number of memory segments */
- bool half_populated = false;
-
/* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to
spd.bin in the case where the SPD data in HW-Info is not available or invalid. */
memset(spd_data, 0, sizeof(spd_data));
@@ -35,5 +32,5 @@
spd_info.spd_spec.spd_index = 0x00;
}
/* Initialize variant specific configurations */
- memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated);
+ memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, false);
}
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58176 )
Change subject: mb/siemens/mc_ehl: Use SPD data from HW-Info in the first place
......................................................................
mb/siemens/mc_ehl: Use SPD data from HW-Info in the first place
The preferred location for the SPD data on mc_ehl based boards is the
HW-Info data structure. Inside this structure there is a field of 128
bytes available for the SPD data. So in order to use it construct a
buffer in memory which is 256 bytes long (as FSP requests minimum 256
bytes for the SPD data) and where the upper 128 bytes are taken from
HW-Info holding the needed timing parameters for LPDDR4.
If there is a case where HW-Info is not accessible or where the
contained SPD data is not valid (by checking the CRC in HW-Info SPD)
fall back to fixed SPD data set in CBFS.
Change-Id: I2b6a1bde0306ba84f5214b876eaf76ca12d8f058
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58176
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---
M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
1 file changed, 22 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
index 259870a..a6ed234 100644
--- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
+++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
@@ -1,20 +1,39 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/mmio.h>
#include <baseboard/variants.h>
+#include <console/console.h>
+#include <device/dram/common.h>
+#include <hwilib.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
+#include <string.h>
+#include <types.h>
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
static struct spd_info spd_info;
const struct mb_cfg *board_cfg = variant_memcfg_config();
+ static uint8_t spd_data[0x100];
+ const char *cbfs_hwi_name = "hwinfo.hex";
/* TODO: Read the resistor strap to get number of memory segments */
bool half_populated = false;
- /* Initialize spd information for LPDDR4x board */
- spd_info.read_type = READ_SPD_CBFS;
- spd_info.spd_spec.spd_index = 0x00;
+ /* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to
+ spd.bin in the case where the SPD data in HW-Info is not available or invalid. */
+ memset(spd_data, 0, sizeof(spd_data));
+ if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) &&
+ (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) &&
+ (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) {
+ spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data;
+ spd_info.spd_spec.spd_data_ptr_info.spd_data_len = sizeof(spd_data);
+ spd_info.read_type = READ_SPD_MEMPTR;
+ } else {
+ printk(BIOS_WARNING, "SPD in HW-Info not valid, fall back to spd.bin!\n");
+ spd_info.read_type = READ_SPD_CBFS;
+ spd_info.spd_spec.spd_index = 0x00;
+ }
/* Initialize variant specific configurations */
memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated);
}
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