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Change subject: soc/amd/common/acpi/upep: Add Low Power State Entry Notifications
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/acpi/upep.asl:
https://review.coreboot.org/c/coreboot/+/58274/comment/b3562edd_eb1d7ce9
PS2, Line 11: ENTRY
> Should we add _LOW_POWER or something to differentiate these from 7 and 8?
I can replace S0IX with "LOW_POWER" to match exactly in the document.
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Change subject: soc/amd/common/acpi/upep: Add Low Power State Entry Notifications
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/acpi/upep.asl:
https://review.coreboot.org/c/coreboot/+/58274/comment/4368bc60_01c8f2f8
PS2, Line 11: ENTRY
Should we add _LOW_POWER or something to differentiate these from 7 and 8?
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Change subject: soc/intel/broadwell/pcie.c: Simplify AND-mask
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS1:
> Hmmm, I'll change it too
Done
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Hello build bot (Jenkins), Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: lynxpoint/broadwell: Correct L1 exit latency with ASPM
......................................................................
lynxpoint/broadwell: Correct L1 exit latency with ASPM
Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit
latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does
the same. Correct the condition accordingly. On Lynx Point, also remove
a now-redundant write to the LCAP register (offset 0x4c).
Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/broadwell/pch/pcie.c
M src/southbridge/intel/lynxpoint/pcie.c
2 files changed, 2 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/57501/3
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Change subject: soc/amd/common/acpi/upep: Add Low Power State Entry Notifications
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/acpi/upep.asl:
https://review.coreboot.org/c/coreboot/+/58274/comment/a0a57fbb_a7c38c2a
PS1, Line 79: PEPD_DSM_LPI_S0IX_ENTRY
> So these need to go in the PEPD_DSM_NOTIFICATIONS_UUID Helper method. […]
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58274
to look at the new patch set (#2).
Change subject: soc/amd/common/acpi/upep: Add Low Power State Entry Notifications
......................................................................
soc/amd/common/acpi/upep: Add Low Power State Entry Notifications
Add support to handle S0ix entry and exit notifications by adding the
corresponding _DSM functions. The function indices are chosen based on
the Modern Standby BIOS Implementation Guide 56358 Rev. 1.04. Inside
the notification functions perform any mainboard specific S0ix entry and
exit actions.
BUG=b:195748540
TEST=Build and boot to OS in Guybrush. Ensure that the notification
functions are invoked on S0ix entry and exit. Perform suspend/resume
cycles for multiple iterations.
Change-Id: I3014551f6e281d466628559453a0141a3dd6abad
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/common/acpi/upep.asl
1 file changed, 28 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/58274/2
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