Attention is currently required from: Felix Held.
Hello build bot (Jenkins), Nico Huber, Arthur Heymans, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57499
to look at the new patch set (#2).
Change subject: soc/intel/broadwell/pcie.c: Simplify AND-mask
......................................................................
soc/intel/broadwell/pcie.c: Simplify AND-mask
There's no need to mask out bit 11, as it is unconditionally set. For
some reason, this changes the resulting coreboot image. Also simplify
another PCI operation with a redundant AND-mask.
Change-Id: I5492acd5f9c61db83a07ce7c1f6b887768c3eadf
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/broadwell/pch/pcie.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/57499/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5492acd5f9c61db83a07ce7c1f6b887768c3eadf
Gerrit-Change-Number: 57499
Gerrit-PatchSet: 2
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newpatchset
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58224 )
Change subject: soc/amd/common/block/include/psp_efs: use unsigned type for bitfield
......................................................................
soc/amd/common/block/include/psp_efs: use unsigned type for bitfield
For 1 bit long bit fields an unsigned type should be used. In this case
uint32_t is used instead of a generic unsigned int for both consistency
reasons with the rest of the file and to clarify that the bits will be
packed into a 32 bit memory location.
TEST=Resulting image of a timeless build for google/guybrush results in
identical binary.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ic630d1709174d90336746bc37da504437c12643c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58224
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/soc/amd/common/block/include/amdblocks/psp_efs.h
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h
index 7afd295..77da70a 100644
--- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h
+++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h
@@ -26,8 +26,8 @@
struct second_gen_efs { /* todo: expand for Server products */
- int gen:1; /* Client products only use bit 0 */
- int reserved:31;
+ uint32_t gen:1; /* Client products only use bit 0 */
+ uint32_t reserved:31;
} __attribute__((packed));
/* Copied from coreboot/util/amdfwtool.h */
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58279 )
Change subject: src/soc/amd/cezanne: enable clock gating
......................................................................
Patch Set 2: Code-Review+2
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58279 )
Change subject: src/soc/amd/cezanne: enable clock gating
......................................................................
Patch Set 2: Code-Review+2
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