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Change subject: src/soc/amd/cezanne: enable clock gating
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/58279/comment/639b7e0d_4cc9905f
PS1, Line 178: t |= ALINKCLK_GATEOFFEN;
: t |= BLINKCLK_GATEOFFEN;
since we're setting these two bits, we should also explicitly set ISACONTROL[abclkgateen]
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Change subject: mb/google/guybrush: Override SPI Fast speeds
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/google/guybrush/verstage.c:
https://review.coreboot.org/c/coreboot/+/58117/comment/03e43a7e_19f18bb8
PS6, Line 45: void mainboard_spi_fast_speed_override(uint8_t *fast_speed)
hrm, can we move this into a file that can be shared between verstage and bootblock?
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Change subject: arch/x86/smbios: Add generation of type 20 table
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Patch Set 8: Code-Review+2
(1 comment)
Patchset:
PS8:
tested on my google/brya0, `dmidecode -t20` shows correct information
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Change subject: soc/amd/common: Add support to read and set SPI speeds from verstage
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Patch Set 6: Code-Review+2
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Change subject: soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init
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Patch Set 4: Code-Review+2
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Change subject: src/soc/amd/cezanne: enable clock gating
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/common/block/spi: Support fast speed override
......................................................................
Patch Set 6:
(1 comment)
File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/58116/comment/c4994bbe_1e6354bd
PS5, Line 53: unused
> i'd still call this parameter fast_speed like in the prototype even though it's unused in the weak i […]
Done
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Change subject: soc/amd/common/block/espi_util: Refactor eSPI Setup
......................................................................
Patch Set 5:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58114/comment/c6e7b8be_b13b0663
PS4, Line 7: ESPI
> eSPI. some more instances below.
Done
File src/soc/amd/cezanne/early_fch.c:
https://review.coreboot.org/c/coreboot/+/58114/comment/3b757df7_59247149
PS4, Line 43: configure_espi();
> see my comments on picasso's early_fch
Done
File src/soc/amd/picasso/early_fch.c:
https://review.coreboot.org/c/coreboot/+/58114/comment/ebb25371_4e6f2548
PS4, Line 48: and SPI Fast speed overrides based on
: board version.
> this isn't related to eSPI and also not what the code is doing
Implicitly board version involves talking with EC which requires ESPI setup. Given that it is optional, I removed it from the comment.
https://review.coreboot.org/c/coreboot/+/58114/comment/975bf856_cadd65b9
PS4, Line 50: configure_espi();
> lpc_early_init needs to be called before configure_espi, since lpc_early_init calls lpc_set_spibase […]
Done
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