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Change subject: arch/x86/smbios: Add generation of type 20 table
......................................................................
Patch Set 7:
(1 comment)
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/58271/comment/5c767ba9_17e56f49
PS7, Line 1037: SMBIOS_MEMORY_DEVICE
`SMBIOS_MEMORY_DEVICE_MAPPED_ADDRESS`
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/common/block/spi: Support fast speed override
......................................................................
soc/amd/common/block/spi: Support fast speed override
Add support to override SPI ROM fast speed based on board version. This
will allow boards to start at lower speeds during bringup and then
switch to higher speeds after assessing the signal integrity. Also
implement a default no-op override.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: Ia8ff3b3bdb53fee142527ae63aa7785945909304
---
M src/soc/amd/common/block/include/amdblocks/spi.h
M src/soc/amd/common/block/spi/fch_spi.c
2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/58116/6
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58114
to look at the new patch set (#5).
Change subject: soc/amd/common/block/espi_util: Refactor eSPI Setup
......................................................................
soc/amd/common/block/espi_util: Refactor eSPI Setup
eSPI is setup in two different locations in bootblock depending on early
port80 routing configuration. Also eSPI is setup in PSP, if verified
boot starts before bootblock. Consolidate all the scenarios by
initializating eSPI very early in fch_pre_init if verified boot starts
after bootblock and eSPI is enabled.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934
---
M src/soc/amd/cezanne/bootblock.c
M src/soc/amd/cezanne/early_fch.c
M src/soc/amd/cezanne/include/soc/southbridge.h
M src/soc/amd/common/block/include/amdblocks/espi.h
M src/soc/amd/common/block/lpc/espi_util.c
M src/soc/amd/picasso/early_fch.c
6 files changed, 19 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/58114/5
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Karthik Ramasubramanian has uploaded a new patch set (#4) to the change originally created by Felix Held. ( https://review.coreboot.org/c/coreboot/+/57782 )
Change subject: soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init
......................................................................
soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init
Since the GPIO mux/control MMIO regions are within the ACPIMMIO region,
we need to call enable_acpimmio_decode_pm04 here first so that accessing
the GPIO registers will work.
BUG=None
TEST=Build and boot to OS in Guybrush.
Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/cezanne/early_fch.c
M src/soc/amd/picasso/early_fch.c
M src/soc/amd/stoneyridge/southbridge.c
3 files changed, 9 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/57782/4
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58271 )
Change subject: arch/x86/smbios: Add generation of type 20 table
......................................................................
Patch Set 6:
(1 comment)
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/58271/comment/c65287ca_0771b239
PS4, Line 1073: +=
> Note that end_addr is start_addr plus the size of the DIMM, so start_addr is doubled each time. […]
you're right, should be =, not +=. will fix
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58274 )
Change subject: soc/amd/common/acpi/upep: Add Low Power State Entry Notifications
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/acpi/upep.asl:
https://review.coreboot.org/c/coreboot/+/58274/comment/c6f09451_577f6bb0
PS1, Line 79: PEPD_DSM_LPI_S0IX_ENTRY
So these need to go in the PEPD_DSM_NOTIFICATIONS_UUID Helper method.
See: Modern Standby BIOS Implementation Guide 56358 Rev. 1.04
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Change subject: arch/x86/smbios: Add generation of type 20 table
......................................................................
Patch Set 6:
(1 comment)
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/58271/comment/5ec3032a_9748cf81
PS4, Line 1073: +=
> there's one type20 table per dimm; start_addr starts at 0 and increments by the size of the dimm for […]
Note that end_addr is start_addr plus the size of the DIMM, so start_addr is doubled each time. I guess you haven't noticed anything wrong because your machines have at most 2 DIMMs, and 0 * 2 = 0 (start_addr begins at 0).
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Hello build bot (Jenkins), Tim Wawrzynczak, Paul Menzel, Angel Pons, Michael Niewöhner,
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Change subject: arch/x86/smbios: Add generation of type 20 table
......................................................................
arch/x86/smbios: Add generation of type 20 table
If available, use data from MEMINFO CBMEM table and saved handles
from type 17/19 tables to generate type 20 (Memory Device Mapped
Address) SMBIOS table.
Windows 10/11 and some other OSes use this table to report the total
memory available on a given device.
Change-Id: I2574d6209d973a8e7f112eb3ef61f5d26986e47b
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/arch/x86/smbios.c
M src/include/smbios.h
2 files changed, 63 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/58271/6
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Change subject: nb/intel/haswell: Add HDAU ACPI device
......................................................................
nb/intel/haswell: Add HDAU ACPI device
The HDAU stub device enables HDMI audio under MacOS.
Change-Id: Ifa2155512dd909a4e4a753f6475541e9410dfe91
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/northbridge/intel/haswell/acpi/hostbridge.asl
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/58272/3
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