coreboot-gerrit October 2021

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Change in coreboot[master]: soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init
by Felix Held (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57782 ) Change subject: soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > this is missing the corresponding change for stoneyridge Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473 Gerrit-Change-Number: 57782 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Oct 2021 17:42:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init
by Felix Held (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57782 ) Change subject: soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/soc/amd/picasso/early_fch.c: https://review.coreboot.org/c/coreboot/+/57782/comment/79d6b1a2_dd7127e1 PS3, Line 45: /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access : the GPIO registers required for eSPI setup. */ > the eSPI setup isn't the only thing that needs this, but i find that the comment suggest that this i […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473 Gerrit-Change-Number: 57782 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Oct 2021 17:42:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/amd/cezanne: enable clock gating
by Name of user not set (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Julian Schroeder. Hello Julian Schroeder, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/58279 to review the following change. Change subject: src/soc/amd/cezanne: enable clock gating ...................................................................... src/soc/amd/cezanne: enable clock gating Enabling clock gating for CGPLL to lower power consumption in S3 and S0i3 states. BUG=b:185273565 TEST=iotools mmio_read32 0xfed80e2c and 0e30 show clk gating enabled. Change-Id: I33cbdeec62e49db90b680da37e5028df03a9c015 Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com> --- M src/soc/amd/cezanne/fch.c M src/soc/amd/cezanne/include/soc/southbridge.h 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/58279/1 diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index ac79cc9..bd08b66 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -169,6 +169,25 @@ misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl); } + +static void cgpll_clock_gate_init(void) +{ + uint32_t t; + + t = misc_read32(MISC_CLKGATEDCNTL); + t |= ALINKCLK_GATEOFFEN; + t |= BLINKCLK_GATEOFFEN; + t |= XTAL_PAD_S3_TURNOFF_EN; + t |= XTAL_PAD_S5_TURNOFF_EN; + misc_write32(MISC_CLKGATEDCNTL, t); + + t = misc_read32(MISC_CGPLL_CONFIGURATION0); + t |= USB_PHY_CMCLK_S3_DIS; + t |= USB_PHY_CMCLK_S0I3_DIS; + t |= USB_PHY_CMCLK_S5_DIS; + misc_write32(MISC_CGPLL_CONFIGURATION0, t); +} + void fch_init(void *chip_info) { fch_init_resets(); @@ -181,6 +200,7 @@ gpp_clk_setup(); fch_clk_output_48Mhz(); + cgpll_clock_gate_init(); } void fch_final(void *chip_info) diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 8a1150e..b031bdf 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -110,6 +110,15 @@ #define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16) #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) +#define MISC_CLKGATEDCNTL 0x2c +#define ALINKCLK_GATEOFFEN BIT(16) +#define BLINKCLK_GATEOFFEN BIT(17) +#define XTAL_PAD_S3_TURNOFF_EN BIT(20) +#define XTAL_PAD_S5_TURNOFF_EN BIT(21) +#define MISC_CGPLL_CONFIGURATION0 0x30 +#define USB_PHY_CMCLK_S3_DIS BIT(8) +#define USB_PHY_CMCLK_S0I3_DIS BIT(9) +#define USB_PHY_CMCLK_S5_DIS BIT(10) void configure_port80_routing_early(void); void fch_pre_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/58279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33cbdeec62e49db90b680da37e5028df03a9c015 Gerrit-Change-Number: 58279 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003801 Gerrit-Reviewer: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/autoport/bd82x6x.go: Fix includes
by Felix Held (Code Review) 13 Oct '21

13 Oct '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58210 ) Change subject: util/autoport/bd82x6x.go: Fix includes ...................................................................... util/autoport/bd82x6x.go: Fix includes Fix include of nvs.h to reflect commit 661ad4666c (ACPI: Select ACPI_SOC_NVS only where suitable); and re-add <device/pci_ops.h>, removed in commit 0aad0531dc (util/autoport/bd82x6x.go: Drop unused includes), as the generated early_init.c uses pci_write_config16(). Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Change-Id: Ic1e97cfa7dce0e4d25f7a37c28d3635bdbf6c2a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58210 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M util/autoport/bd82x6x.go 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index ad8918a..f00c89f 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -296,6 +296,7 @@ sb.WriteString(` #include <bootblock_common.h> +#include <device/pci_ops.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -359,7 +360,7 @@ Add_gpl(gnvs) gnvs.WriteString(`#include <acpi/acpi_gnvs.h> -#include <southbridge/intel/bd82x6x/nvs.h> +#include <soc/nvs.h> /* FIXME: check this function. */ void mainboard_fill_gnvs(struct global_nvs *gnvs) 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e97cfa7dce0e4d25f7a37c28d3635bdbf6c2a5 Gerrit-Change-Number: 58210 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSR
by Felix Held (Code Review) 13 Oct '21

13 Oct '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58220 ) Change subject: soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSR ...................................................................... soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSR Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only. Change-Id: Ia196906d3c2636742ae90160a224354e8df7863a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58220 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/cannonlake/cpu.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 821694e..99fcadd 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -62,8 +62,9 @@ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); if (cfg->max_package_c_state && (msr.lo & 0xf) >= cfg->max_package_c_state) { msr.lo = (msr.lo & ~0xf) | ((cfg->max_package_c_state - 1) & 0xf); - wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); } + msr.lo |= CST_CFG_LOCK_MASK; + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* C-state Interrupt Response Latency Control 0 - package C3 latency */ msr.hi = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/58220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia196906d3c2636742ae90160a224354e8df7863a Gerrit-Change-Number: 58220 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/*/cpu.c: Add missing space in comment
by Felix Held (Code Review) 13 Oct '21

13 Oct '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58219 ) Change subject: soc/intel/*/cpu.c: Add missing space in comment ...................................................................... soc/intel/*/cpu.c: Add missing space in comment Add a space before the `*/` C-style comment ending. Change-Id: Ic8928286c8237808b9e380e4393078792589615d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58219 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 7 files changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 2f1ac8e..801d10d 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -55,7 +55,7 @@ /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 5ac7d5a..821694e 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -50,7 +50,7 @@ /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 6d86b0c..0788c67 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -48,7 +48,7 @@ /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 6c3365b..3ca2172 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -48,7 +48,7 @@ /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 86077ff..a58fe55 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -48,7 +48,7 @@ /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 19f2e3a..3abf19b 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -49,7 +49,7 @@ wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 18); /* Enable Energy/Performance Bias control */ msr.lo &= ~POWER_CTL_C1E_MASK; /* Disable C1E */ msr.lo |= (1 << 23); /* Lock it */ diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 7bb9e61..084b5d6 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -54,7 +54,7 @@ /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } -- To view, visit https://review.coreboot.org/c/coreboot/+/58219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8928286c8237808b9e380e4393078792589615d Gerrit-Change-Number: 58219 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Add hook function to return EC in RW status
by Anil Kumar K (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Bora Guvendik, Selma Bensaid, Hsuan-ting Chen, Paul Menzel, Tim Wawrzynczak, Bernardo Perez Priego. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58099 ) Change subject: mb/intel/adlrvp: Add hook function to return EC in RW status ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58099/comment/395a1a50_8d290456 PS7, Line 9: EC_IN_RW signal from EC GPIO is connected to GPIO E7 : of SOC. The function reads this GPIO to check if EC is in : RW (un trusted) or RO (trusted) > Ack i updated the commit message to text as suggested. But the formatting on the Gerrit seems to not preserve that. When i do Git log on my host i see it being as expected -- To view, visit https://review.coreboot.org/c/coreboot/+/58099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 Gerrit-Change-Number: 58099 Gerrit-PatchSet: 9 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Comment-Date: Tue, 12 Oct 2021 17:11:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/smbios: Add generation of type 20 table
by Angel Pons (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58271 ) Change subject: arch/x86/smbios: Add generation of type 20 table ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2574d6209d973a8e7f112eb3ef61f5d26986e47b Gerrit-Change-Number: 58271 Gerrit-PatchSet: 8 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 12 Oct 2021 16:46:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/smbios: Add generation of type 20 table
by build bot (Jenkins) (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Angel Pons, Michael Niewöhner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58271 ) Change subject: arch/x86/smbios: Add generation of type 20 table ...................................................................... Patch Set 8: (1 comment) File src/arch/x86/smbios.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130301): https://review.coreboot.org/c/coreboot/+/58271/comment/ef9bea54_d65dc337 PS8, Line 1037: struct smbios_type20 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE_MAPPED_ADDRESS, line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/58271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2574d6209d973a8e7f112eb3ef61f5d26986e47b Gerrit-Change-Number: 58271 Gerrit-PatchSet: 8 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 12 Oct 2021 16:42:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/smbios: Add generation of type 20 table
by Matt DeVillier (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Angel Pons, Michael Niewöhner. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58271 ) Change subject: arch/x86/smbios: Add generation of type 20 table ...................................................................... Patch Set 8: (2 comments) File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/58271/comment/16f1d85d_3fcf6dd3 PS4, Line 1073: += > you're right, should be =, not +=. […] Done File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/58271/comment/65b3b58b_3baac1d4 PS7, Line 1037: SMBIOS_MEMORY_DEVICE > `SMBIOS_MEMORY_DEVICE_MAPPED_ADDRESS` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2574d6209d973a8e7f112eb3ef61f5d26986e47b Gerrit-Change-Number: 58271 Gerrit-PatchSet: 8 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 12 Oct 2021 16:37:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit October 2021