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Change subject: arch/x86/smbios: Add generation of type 20 table
......................................................................
Patch Set 4:
(2 comments)
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/58271/comment/6aed41c9_d8b6eb99
PS4, Line 1073: (end_addr + 1)
> nit: braces not needed
Ack
https://review.coreboot.org/c/coreboot/+/58271/comment/7e899bee_2a3e5dc2
PS4, Line 1073: +=
> Is the `+=` correct? I'd use `=` instead.
there's one type20 table per dimm; start_addr starts at 0 and increments by the size of the dimm for each loop iteration
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Change subject: arch/x86/smbios: Add generation of type 20 table
......................................................................
Patch Set 4:
(2 comments)
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/58271/comment/654ec24f_b4e0e2c9
PS4, Line 1073: (end_addr + 1)
nit: braces not needed
https://review.coreboot.org/c/coreboot/+/58271/comment/6b730fb1_f5646b4c
PS4, Line 1073: +=
Is the `+=` correct? I'd use `=` instead.
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Change subject: nb/haswell: Add HDAU ACPI device
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58272/comment/2dbe44d4_765d27cd
PS1, Line 7: nb/haswell/acpi
> `nb/intel/haswell`, ACPI is already mentioned later.
Done
https://review.coreboot.org/c/coreboot/+/58272/comment/24d173fe_08c3b667
PS1, Line 9: MacOS
> missing a period.
Done
https://review.coreboot.org/c/coreboot/+/58272/comment/5fc6d7e7_5bcc522b
PS1, Line 9: The HDAU stub device enables HDMI audio under MacOS
> Do you have any references to this issue?
just various posts on reddit, hackintosh forums, and https://github.com/MrChromebox/firmware/issues/5
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Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58272
to look at the new patch set (#2).
Change subject: nb/haswell: Add HDAU ACPI device
......................................................................
nb/haswell: Add HDAU ACPI device
The HDAU stub device enables HDMI audio under MacOS.
Change-Id: Ifa2155512dd909a4e4a753f6475541e9410dfe91
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/northbridge/intel/haswell/acpi/hostbridge.asl
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/58272/2
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Change subject: mb/google/wyvern: use SaGv_FixedHigh
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
> Seems OK to me, agree it seems unnecessary for a desktop system. […]
Disabled and FixedHigh seem to do the same thing
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Change subject: nb/haswell/acpi: Add HDAU ACPI device
......................................................................
Patch Set 1: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58272/comment/5fc21d10_55cc9e86
PS1, Line 7: nb/haswell/acpi
`nb/intel/haswell`, ACPI is already mentioned later.
https://review.coreboot.org/c/coreboot/+/58272/comment/ba1facb6_efdba8a0
PS1, Line 9: The HDAU stub device enables HDMI audio under MacOS
Do you have any references to this issue?
https://review.coreboot.org/c/coreboot/+/58272/comment/428a8233_d43debc8
PS1, Line 9: MacOS
missing a period.
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Change subject: libpayload: Add unit-tests framework and first test case
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58242/comment/47a77941_f7edfa63
PS3, Line 9: framewok
framework
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Change subject: tests: Add lib/lzma-test test case
......................................................................
Patch Set 9: Code-Review+1
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Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58275 )
Change subject: mb/google/guybrush: Assert WWAN_AUX_RST_L on S0i3 entry
......................................................................
mb/google/guybrush: Assert WWAN_AUX_RST_L on S0i3 entry
Currently WWAN_AUX_RST_L is in S5 domain and does not get asserted on
S0i3 entry. Based on the schematics, the pull-down on that signal leads
to 10 mW power leakage on S0i3 entry. Assert the signal on S0i3 entry to
achieve some power savings and de-assert it on S0i3 exit.
BUG=b:195748540
TEST=Build and boot to OS in Guybrush. Ensure that the signal gets
asserted on S0i3 entry and de-asserted on S0i3 exit. Trigger
suspend/resume cycles and ensure that the WWAN module is enumerated
after each cycle.
Change-Id: I43c8655ee5209779748e4365db973e094cb08aca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/guybrush/mainboard.c
1 file changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/58275/1
diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c
index 3626157..39ef2a0 100644
--- a/src/mainboard/google/guybrush/mainboard.c
+++ b/src/mainboard/google/guybrush/mainboard.c
@@ -13,11 +13,13 @@
#include <vendorcode/google/chromeos/chromeos.h>
#define BACKLIGHT_GPIO GPIO_129
+#define WWAN_AUX_RST_GPIO GPIO_18
#define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN"
#define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS"
#define METHOD_MAINBOARD_INI "\\_SB.MINI"
#define METHOD_MAINBOARD_WAK "\\_SB.MWAK"
#define METHOD_MAINBOARD_PTS "\\_SB.MPTS"
+#define METHOD_MAINBOARD_S0X "\\_SB.MS0X"
/*
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@@ -151,6 +153,31 @@
acpigen_pop_len();
}
+static void mainboard_assert_wwan_aux_reset(void)
+{
+ if (variant_has_pcie_wwan())
+ acpigen_soc_clear_tx_gpio(WWAN_AUX_RST_GPIO);
+}
+
+static void mainboard_deassert_wwan_aux_reset(void)
+{
+ if (variant_has_pcie_wwan())
+ acpigen_soc_set_tx_gpio(WWAN_AUX_RST_GPIO);
+}
+
+static void mainboard_write_ms0x(void)
+{
+ acpigen_write_method_serialized(METHOD_MAINBOARD_S0X, 1);
+ /* S0ix Entry */
+ acpigen_write_if_lequal_op_int(ARG0_OP, 1);
+ mainboard_assert_wwan_aux_reset();
+ /* S0ix Exit */
+ acpigen_write_else();
+ mainboard_deassert_wwan_aux_reset();
+ acpigen_pop_len();
+ acpigen_pop_len();
+}
+
static void mainboard_fill_ssdt(const struct device *dev)
{
mainboard_write_blken();
@@ -158,6 +185,7 @@
mainboard_write_mini();
mainboard_write_mpts();
mainboard_write_mwak();
+ mainboard_write_ms0x();
}
static void mainboard_enable(struct device *dev)
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