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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57951
to look at the new patch set (#4).
Change subject: Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
......................................................................
Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
This reverts commit 6260bf712a836762b18d80082505e981e040f4bc.
Reason for revert: This CL did not handle Intel GPIO correctly. We need
to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel
SoC.
Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org>
Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75
---
M src/include/bootmode.h
M src/mainboard/google/asurada/chromeos.c
M src/mainboard/google/auron/chromeos.c
M src/mainboard/google/beltino/chromeos.c
M src/mainboard/google/brya/chromeos.c
M src/mainboard/google/butterfly/chromeos.c
M src/mainboard/google/cherry/chromeos.c
M src/mainboard/google/cyan/chromeos.c
M src/mainboard/google/daisy/chromeos.c
M src/mainboard/google/dedede/chromeos.c
M src/mainboard/google/deltaur/chromeos.c
M src/mainboard/google/drallion/chromeos.c
M src/mainboard/google/eve/chromeos.c
M src/mainboard/google/fizz/chromeos.c
M src/mainboard/google/foster/chromeos.c
M src/mainboard/google/gale/chromeos.c
M src/mainboard/google/glados/chromeos.c
M src/mainboard/google/gru/chromeos.c
M src/mainboard/google/guybrush/chromeos.c
M src/mainboard/google/hatch/chromeos.c
M src/mainboard/google/herobrine/chromeos.c
M src/mainboard/google/jecht/chromeos.c
M src/mainboard/google/kahlee/chromeos.c
M src/mainboard/google/kukui/chromeos.c
M src/mainboard/google/link/chromeos.c
M src/mainboard/google/mistral/chromeos.c
M src/mainboard/google/nyan/chromeos.c
M src/mainboard/google/nyan_big/chromeos.c
M src/mainboard/google/nyan_blaze/chromeos.c
M src/mainboard/google/oak/chromeos.c
M src/mainboard/google/octopus/chromeos.c
M src/mainboard/google/parrot/chromeos.c
M src/mainboard/google/peach_pit/chromeos.c
M src/mainboard/google/poppy/chromeos.c
M src/mainboard/google/rambi/chromeos.c
M src/mainboard/google/reef/chromeos.c
M src/mainboard/google/sarien/chromeos.c
M src/mainboard/google/slippy/chromeos.c
M src/mainboard/google/smaug/chromeos.c
M src/mainboard/google/storm/chromeos.c
M src/mainboard/google/trogdor/chromeos.c
M src/mainboard/google/veyron/chromeos.c
M src/mainboard/google/veyron_mickey/chromeos.c
M src/mainboard/google/veyron_rialto/chromeos.c
M src/mainboard/google/volteer/chromeos.c
M src/mainboard/google/zork/chromeos.c
M src/security/vboot/bootmode.c
M src/security/vboot/vboot_logic.c
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/skylake/Makefile.inc
51 files changed, 0 insertions(+), 323 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/57951/4
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Change subject: mb/google/guybrush/var/nipperkin: update MAX98360 HID to MX98360A
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/common/block/spi: Support fast speed override
......................................................................
Patch Set 5: Code-Review+1
(2 comments)
Patchset:
PS5:
since i don't expect that we'll run into the need to override the other spi speed settings with board=specific values that can only be determined during runtime, i think this is a good approach
File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/58116/comment/4fc748b8_366f9816
PS5, Line 53: unused
i'd still call this parameter fast_speed like in the prototype even though it's unused in the weak implementation of this function. just that it's clear what that's normally used for
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Change subject: drivers/pc80/tpm: Use stopwatch for timeout-loops
......................................................................
Patch Set 1:
(1 comment)
File src/drivers/pc80/tpm/tis.c:
https://review.coreboot.org/c/coreboot/+/58240/comment/28b9aa08_f3840e27
PS1, Line 257: udelay(1); /* 1 us */
> I'd leave the original delay value as-is. It's been tried and tested.
OK, will do!
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Change subject: drivers/pc80/tpm: Use stopwatch for timeout-loops
......................................................................
Patch Set 1:
(1 comment)
File src/drivers/pc80/tpm/tis.c:
https://review.coreboot.org/c/coreboot/+/58240/comment/3112ec4b_a1077026
PS1, Line 257: udelay(1); /* 1 us */
> Agree, this can easy be the case for a TPM, too. […]
I'd leave the original delay value as-is. It's been tried and tested.
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Change subject: drivers/pc80/tpm: Use stopwatch for timeout-loops
......................................................................
Patch Set 1:
(1 comment)
File src/drivers/pc80/tpm/tis.c:
https://review.coreboot.org/c/coreboot/+/58240/comment/e9a00812_730b3bfc
PS1, Line 257: udelay(1); /* 1 us */
> Polling too fast is an issue when reading the value interrupts the task one is waiting to be done. […]
Agree, this can easy be the case for a TPM, too. Should we then add a udelay(10) instead to relax a possible tight timing inside the TPM? In the worst case we would waste 9 us here then.
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Change subject: soc/amd/common/block/include/psp_efs: use unsigned type for bitfield
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/psp_efs.h:
https://review.coreboot.org/c/coreboot/+/58224/comment/6180036f_efc3a0e0
PS1, Line 29: uint32_t
> mostly for consistency with the rest of the file, but also to clarify that the bits will be packed i […]
added my reasoning for this to the commit message. at least i think that's what you'd like me to do here
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58224
to look at the new patch set (#2).
Change subject: soc/amd/common/block/include/psp_efs: use unsigned type for bitfield
......................................................................
soc/amd/common/block/include/psp_efs: use unsigned type for bitfield
For 1 bit long bit fields an unsigned type should be used. In this case
uint32_t is used instead of a generic unsigned int for both consistency
reasons with the rest of the file and to clarify that the bits will be
packed into a 32 bit memory location.
TEST=Resulting image of a timeless build for google/guybrush results in
identical binary.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ic630d1709174d90336746bc37da504437c12643c
---
M src/soc/amd/common/block/include/amdblocks/psp_efs.h
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/58224/2
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Change subject: soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init
......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS3:
this is missing the corresponding change for stoneyridge
File src/soc/amd/picasso/early_fch.c:
https://review.coreboot.org/c/coreboot/+/57782/comment/7f14fa30_5275bb7f
PS3, Line 45: /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
: the GPIO registers required for eSPI setup. */
the eSPI setup isn't the only thing that needs this, but i find that the comment suggest that this is only or at least primarily for the eSPI GPIO setup
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