coreboot-gerrit October 2021

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Change in coreboot[master]: soc/intel/skylake: switch to common GNVS
by Michael Niewöhner (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Felix Singer, Nico Huber, Furquan Shaikh, Michał Żygowski, Tim Wawrzynczak, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Piotr Król, Wim Vervoorn. Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Frans Hendriks, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Piotr Król, Nico Huber, Michał Żygowski, Tim Wawrzynczak, Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57946 to look at the new patch set (#13). Change subject: soc/intel/skylake: switch to common GNVS ...................................................................... soc/intel/skylake: switch to common GNVS Switch to common GNVS. No additional fields to those being present in common GNVS are used by any SKL/KBL device. Thus, they're dropped completely. Change-Id: I87ab4ab05f6c081697801276a744d49e9e1908e0 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/51nb/x210/dsdt.asl M src/mainboard/asrock/h110m/dsdt.asl M src/mainboard/clevo/kbl-u/dsdt.asl M src/mainboard/facebook/monolith/dsdt.asl M src/mainboard/google/eve/dsdt.asl M src/mainboard/google/fizz/dsdt.asl M src/mainboard/google/glados/dsdt.asl M src/mainboard/google/poppy/dsdt.asl M src/mainboard/hp/280_g2/dsdt.asl M src/mainboard/intel/kblrvp/dsdt.asl M src/mainboard/intel/kunimitsu/dsdt.asl M src/mainboard/intel/saddlebrook/dsdt.asl M src/mainboard/kontron/bsl6/dsdt.asl M src/mainboard/libretrend/lt1000/dsdt.asl M src/mainboard/protectli/vault_kbl/dsdt.asl M src/mainboard/purism/librem_skl/dsdt.asl M src/mainboard/razer/blade_stealth_kbl/dsdt.asl M src/mainboard/supermicro/x11-lga1151-series/dsdt.asl D src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/include/soc/nvs.h 20 files changed, 19 insertions(+), 109 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/57946/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/57946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87ab4ab05f6c081697801276a744d49e9e1908e0 Gerrit-Change-Number: 57946 Gerrit-PatchSet: 13 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: add SGX fields to GNVS
by Michael Niewöhner (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Felix Singer, Nico Huber, Furquan Shaikh, Angel Pons, Kyösti Mälkki, Patrick Rudolph. Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Angel Pons, Kyösti Mälkki, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57947 to look at the new patch set (#11). Change subject: soc/intel/common: add SGX fields to GNVS ...................................................................... soc/intel/common: add SGX fields to GNVS Add the SGX fields to the GNVS. This is required for Skylake to use the common GNVS. Change-Id: I0077260b7eb1bc2b2fe2af69ac039b38ca0e7423 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/nvs.h 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/57947/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/57947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0077260b7eb1bc2b2fe2af69ac039b38ca0e7423 Gerrit-Change-Number: 57947 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: drop P_BLK support
by Michael Niewöhner (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Mariusz Szafrański, Jonathan Zhang, Angel Pons, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Suresh Bellampalli, Christian Walter, Vanessa Eusebio, Michal Motyl, Tim Chu. Hello build bot (Jenkins), Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58096 to look at the new patch set (#8). Change subject: soc/intel: drop P_BLK support ...................................................................... soc/intel: drop P_BLK support P_BLK is legacy and superseded by ACPI _CST. Also, the implementation for most platforms in soc/intel is broken. Thus, drop it. For APL the IO redirection is kept since it's used as replacement for the broken MWAIT instructions. Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/fadt.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/skylake/fadt.c M src/soc/intel/xeon_sp/include/soc/msr.h M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/skx/soc_acpi.c 14 files changed, 9 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/58096/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/58096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36 Gerrit-Change-Number: 58096 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: switch to common ACPI code
by Michael Niewöhner (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Felix Singer, Furquan Shaikh, Benjamin Doron, Paul Menzel, Mimoja, Subrata Banik, Arthur Heymans, Michael Niewöhner, Kyösti Mälkki, Matthew Garrett, Patrick Rudolph, Aaron Durbin, Tim Crawford, Nico Huber, Tim Wawrzynczak, Maxim Polyakov, Michal Zygowski, Wim Vervoorn. Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Benjamin Doron, Matt DeVillier, Paul Menzel, Mimoja, Subrata Banik, Arthur Heymans, Kyösti Mälkki, Matthew Garrett, Patrick Rudolph, Aaron Durbin, Tim Crawford, Nico Huber, Tim Wawrzynczak, Maxim Polyakov, Michal Zygowski, Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44138 to look at the new patch set (#23). Change subject: soc/intel/skylake: switch to common ACPI code ...................................................................... soc/intel/skylake: switch to common ACPI code Use the common ACPI code to reduce code duplication. Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/supermicro/x11-lga1151-series/fadt.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/fadt.c D src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/include/soc/pmc.h M src/soc/intel/skylake/include/soc/ramstage.h 9 files changed, 63 insertions(+), 423 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44138/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/44138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40 Gerrit-Change-Number: 44138 Gerrit-PatchSet: 23 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mimoja <coreboot(a)mimoja.de> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Matthew Garrett <mjg59(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: drop P_BLK support
by Michael Niewöhner (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Mariusz Szafrański, Jonathan Zhang, Angel Pons, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Suresh Bellampalli, Christian Walter, Vanessa Eusebio, Michal Motyl, Tim Chu. Hello build bot (Jenkins), Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58096 to look at the new patch set (#7). Change subject: soc/intel: drop P_BLK support ...................................................................... soc/intel: drop P_BLK support P_BLK is legacy and superseeded by ACPI _CST. Also, the implementation for most platforms in soc/intel is broken. Thus, drop it. For APL the IO redirection is kept since it's used as replacement for the broken MWAIT instructions. Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/fadt.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/skylake/fadt.c M src/soc/intel/xeon_sp/include/soc/msr.h M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/skx/soc_acpi.c 14 files changed, 9 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/58096/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/58096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36 Gerrit-Change-Number: 58096 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: drop P_BLK support
by Michael Niewöhner (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Mariusz Szafrański, Jonathan Zhang, Angel Pons, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Suresh Bellampalli, Christian Walter, Vanessa Eusebio, Michal Motyl, Tim Chu. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58096 ) Change subject: soc/intel: drop P_BLK support ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58096/comment/c96383a0_97152fed PS5, Line 9: ee > Just one `e` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36 Gerrit-Change-Number: 58096 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 12 Oct 2021 18:27:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: drop P_BLK support
by Michael Niewöhner (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Suresh Bellampalli, Christian Walter, Vanessa Eusebio, Michal Motyl, Tim Chu. Hello build bot (Jenkins), Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58096 to look at the new patch set (#6). Change subject: soc/intel: drop P_BLK support ...................................................................... soc/intel: drop P_BLK support P_BLK is legacy and superseded by ACPI _CST. Also, the implementation for most platforms in soc/intel is broken. Thus, drop it. For APL the IO redirection is kept since it's used as replacement for the broken MWAIT instructions. Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/fadt.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/skylake/fadt.c M src/soc/intel/xeon_sp/include/soc/msr.h M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/skx/soc_acpi.c 14 files changed, 10 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/58096/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36 Gerrit-Change-Number: 58096 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: replace dt option PmTimerDisabled by Kconfig
by Michael Niewöhner (Code Review) 13 Oct '21

13 Oct '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58016 ) Change subject: soc/intel: replace dt option PmTimerDisabled by Kconfig ...................................................................... soc/intel: replace dt option PmTimerDisabled by Kconfig Replace the dt option `PmTimerDisabled` with use of the Kconfig option `USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer. A default value representing the prior devicetree value was added to the boards system76/{lemp10,galp5,darp7}, so this change will not alter behaviour. Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/system76/darp7/Kconfig M src/mainboard/system76/darp7/devicetree.cb M src/mainboard/system76/galp5/Kconfig M src/mainboard/system76/galp5/devicetree.cb M src/mainboard/system76/lemp10/Kconfig M src/mainboard/system76/lemp10/devicetree.cb M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/finalize.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/finalize.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/finalize.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/finalize.c 21 files changed, 31 insertions(+), 61 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Lance Zhao: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Tim Crawford: Looks good to me, but someone else must approve diff --git a/src/mainboard/system76/darp7/Kconfig b/src/mainboard/system76/darp7/Kconfig index 4af6768..2c9cbc4 100644 --- a/src/mainboard/system76/darp7/Kconfig +++ b/src/mainboard/system76/darp7/Kconfig @@ -52,4 +52,8 @@ config UART_FOR_CONSOLE default 2 +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index c5297dc..1397097 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -26,10 +26,6 @@ .tdp_pl2_override = 40, }" -# Finalize (soc/intel/tigerlake/finalize.c) - # PM Timer Disabled, saves power - register "PmTimerDisabled" = "1" - # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # Enable C6 DRAM register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/galp5/Kconfig b/src/mainboard/system76/galp5/Kconfig index 79978c9..534c253 100644 --- a/src/mainboard/system76/galp5/Kconfig +++ b/src/mainboard/system76/galp5/Kconfig @@ -53,4 +53,8 @@ config UART_FOR_CONSOLE default 2 +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index 322a2e1..cf3a75e 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -26,10 +26,6 @@ .tdp_pl2_override = 51, }" -# Finalize (soc/intel/tigerlake/finalize.c) - # PM Timer Disabled, saves power - register "PmTimerDisabled" = "1" - # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # Enable C6 DRAM register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/lemp10/Kconfig b/src/mainboard/system76/lemp10/Kconfig index 637c902..1b6eec4 100644 --- a/src/mainboard/system76/lemp10/Kconfig +++ b/src/mainboard/system76/lemp10/Kconfig @@ -52,4 +52,8 @@ config UART_FOR_CONSOLE default 2 +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index f286ab5..1362b3d 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -26,10 +26,6 @@ .tdp_pl2_override = 30, }" -# Finalize (soc/intel/tigerlake/finalize.c) - # PM Timer Disabled, saves power - register "PmTimerDisabled" = "1" - # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # Enable C6 DRAM register "enable_c6dram" = "1" diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index d3a41ee..e98878f 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -41,6 +41,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 270400b..699626b 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -286,7 +286,7 @@ /* Enable C6 DRAM */ uint8_t enable_c6dram; - uint8_t PmTimerDisabled; + /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index c821e25..4ef572b 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -50,7 +50,7 @@ static void pch_finalize(void) { - config_t *config; + config_t *config = config_of_soc(); /* TCO Lock down */ tco_lockdown(); @@ -58,13 +58,12 @@ /* TODO: Add Thermal Configuration */ /* - * Disable ACPI PM timer based on dt policy + * Disable ACPI PM timer based on Kconfig * * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO */ - config = config_of_soc(); - if (config->PmTimerDisabled) + if (!CONFIG(USE_PM_ACPI_TIMER)) pmc_disable_acpi_timer(); pch_handle_sideband(config); diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 6d44cd6..07af2fa 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -31,6 +31,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index b36d67a..e18e52d 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -236,8 +236,6 @@ /* Enable C6 DRAM */ uint8_t enable_c6dram; - uint8_t PmTimerDisabled; - /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index 3d1430f..ad3b4ef 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -24,26 +24,18 @@ static void pch_finalize(void) { - config_t *config; - /* TCO Lock down */ tco_lockdown(); /* TODO: Add Thermal Configuration */ /* - * Disable ACPI PM timer based on dt policy + * Disable ACPI PM timer based on Kconfig * * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO - * - * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is - * just required to get to chip config. PCH_DEV_PMC is hidden by this - * point and hence removed from the root bus. pcidev_path_on_root thus - * returns NULL for PCH_DEV_PMC device. */ - config = config_of_soc(); - if (config->PmTimerDisabled) + if (!CONFIG(USE_PM_ACPI_TIMER)) pmc_disable_acpi_timer(); pmc_clear_pmcon_sts(); diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 8f6303d..74bae9c 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -31,6 +31,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM select CPU_INTEL_COMMON diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index bef9adb..9adc5b0 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -144,8 +144,6 @@ /* Enable C6 DRAM */ uint8_t enable_c6dram; - uint8_t PmTimerDisabled; - /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index bc8386a..f828cc4 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -40,7 +40,7 @@ static void pch_finalize(void) { - config_t *config; + config_t *config = config_of_soc(); /* TCO Lock down */ tco_lockdown(); @@ -55,18 +55,12 @@ pch_thermal_configuration(); /* - * Disable ACPI PM timer based on dt policy + * Disable ACPI PM timer based on Kconfig * * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO - * - * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is - * just required to get to chip config. PCH_DEV_PMC is hidden by this - * point and hence removed from the root bus. pcidev_path_on_root thus - * returns NULL for PCH_DEV_PMC device. */ - config = config_of_soc(); - if (config->PmTimerDisabled) + if (!CONFIG(USE_PM_ACPI_TIMER)) pmc_disable_acpi_timer(); pch_handle_sideband(config); diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 3f9014c..690df0c 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -32,6 +32,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 3d680d3..87a98fb 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -152,8 +152,6 @@ /* Enable C6 DRAM */ uint8_t enable_c6dram; - uint8_t PmTimerDisabled; - /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index a60e719..9aef9eb 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -44,7 +44,7 @@ { uint32_t reg32; uint8_t *pmcbase; - config_t *config; + config_t *config = config_of_soc(); /* TCO Lock down */ tco_lockdown(); @@ -52,18 +52,12 @@ /* TODO: Add Thermal Configuration */ /* - * Disable ACPI PM timer based on dt policy + * Disable ACPI PM timer based on Kconfig * * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO - * - * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is - * just required to get to chip config. PCH_DEV_PMC is hidden by this - * point and hence removed from the root bus. pcidev_path_on_root thus - * returns NULL for PCH_DEV_PMC device. */ - config = config_of_soc(); - if (config->PmTimerDisabled) + if (!CONFIG(USE_PM_ACPI_TIMER)) pmc_disable_acpi_timer(); pmcbase = pmc_mmio_regs(); diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 3739178..fe7805a 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -40,6 +40,7 @@ select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_2 + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 465dea2..f0858db 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -289,7 +289,7 @@ /* Enable C6 DRAM */ uint8_t enable_c6dram; - uint8_t PmTimerDisabled; + /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 6ed60e7..26cba96 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -30,8 +30,6 @@ static void pch_finalize(void) { - config_t *config; - /* TCO Lock down */ tco_lockdown(); @@ -42,14 +40,8 @@ * * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO - * - * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is - * just required to get to chip config. PCH_DEV_PMC is hidden by this - * point and hence removed from the root bus. pcidev_path_on_root thus - * returns NULL for PCH_DEV_PMC device. */ - config = config_of_soc(); - if (config->PmTimerDisabled) + if (!CONFIG(USE_PM_ACPI_TIMER)) pmc_disable_acpi_timer(); pmc_clear_pmcon_sts(); -- To view, visit https://review.coreboot.org/c/coreboot/+/58016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947 Gerrit-Change-Number: 58016 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/espi_util: Refactor eSPI Setup
by Karthik Ramasubramanian (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58114 to look at the new patch set (#6). Change subject: soc/amd/common/block/espi_util: Refactor eSPI Setup ...................................................................... soc/amd/common/block/espi_util: Refactor eSPI Setup eSPI is setup in two different locations in bootblock depending on early port80 routing configuration. Also eSPI is setup in PSP, if verified boot starts before bootblock. Consolidate all the scenarios by initializating eSPI very early in fch_pre_init if verified boot starts after bootblock and eSPI is enabled. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 --- M src/soc/amd/cezanne/bootblock.c M src/soc/amd/cezanne/early_fch.c M src/soc/amd/cezanne/include/soc/southbridge.h M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/picasso/early_fch.c 5 files changed, 17 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/58114/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 Gerrit-Change-Number: 58114 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/soc/amd/cezanne: enable clock gating
by Felix Held (Code Review) 13 Oct '21

13 Oct '21

Attention is currently required from: Marshall Dawson, Name of user not set #1003801, Julian Schroeder. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58279 ) Change subject: src/soc/amd/cezanne: enable clock gating ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/cezanne/include/soc/southbridge.h: https://review.coreboot.org/c/coreboot/+/58279/comment/0f05d118_5764264d PS1, Line 113: #define MISC_CLKGATEDCNTL 0x2c : #define ALINKCLK_GATEOFFEN BIT(16) : #define BLINKCLK_GATEOFFEN BIT(17) : #define XTAL_PAD_S3_TURNOFF_EN BIT(20) : #define XTAL_PAD_S5_TURNOFF_EN BIT(21) : #define MISC_CGPLL_CONFIGURATION0 0x30 : #define USB_PHY_CMCLK_S3_DIS BIT(8) : #define USB_PHY_CMCLK_S0I3_DIS BIT(9) : #define USB_PHY_CMCLK_S5_DIS BIT(10) would be good to move those register and bit definitions so that the registers are ordered; so this should be added above MISC_CLK_CNTL0 -- To view, visit https://review.coreboot.org/c/coreboot/+/58279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33cbdeec62e49db90b680da37e5028df03a9c015 Gerrit-Change-Number: 58279 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003801 Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Name of user not set #1003801 Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Oct 2021 18:14:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2021