Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58196 )
Change subject: mb/google/dedede/var/sasukette: Generate SPD ID for Samsung K4U6E3S4AB-MGCL
......................................................................
mb/google/dedede/var/sasukette: Generate SPD ID for Samsung K4U6E3S4AB-MGCL
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
BUG=b:202480992
TEST=emerge-dedede coreboot
Signed-off-by: Zhi Li <lizhi7(a)huaqin.corp-partner.google.com>
Change-Id: I811f32defd50a940a09f238d38c962d2caf42855
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58196
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc
M src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt
3 files changed, 3 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Karthik Ramasubramanian: Looks good to me, approved
Weimin Wu: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc b/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc
index 490e591..05ff304 100644
--- a/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc
+++ b/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc
@@ -4,4 +4,4 @@
# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/sasukette/memory src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt
SPD_SOURCES =
-SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR
+SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL
diff --git a/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt
index b02dcd7..cb4801e 100644
--- a/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt
@@ -5,3 +5,4 @@
DRAM Part Name ID to assign
K4U6E3S4AA-MGCR 0 (0000)
+K4U6E3S4AB-MGCL 0 (0000)
diff --git a/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt
index be1daed..476f0f5 100644
--- a/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt
@@ -10,3 +10,4 @@
# Part Name
K4U6E3S4AA-MGCR
+K4U6E3S4AB-MGCL
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Change subject: soc/amd/common/acpi/upep: Add Low Power State Entry Notifications
......................................................................
Patch Set 3: Code-Review+2
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58274
to look at the new patch set (#3).
Change subject: soc/amd/common/acpi/upep: Add Low Power State Entry Notifications
......................................................................
soc/amd/common/acpi/upep: Add Low Power State Entry Notifications
Add support to handle S0ix entry and exit notifications by adding the
corresponding _DSM functions. The function indices are chosen based on
the Modern Standby BIOS Implementation Guide 56358 Rev. 1.04. Inside
the notification functions perform any mainboard specific S0ix entry and
exit actions.
BUG=b:195748540
TEST=Build and boot to OS in Guybrush. Ensure that the notification
functions are invoked on S0ix entry and exit. Perform suspend/resume
cycles for multiple iterations.
Change-Id: I3014551f6e281d466628559453a0141a3dd6abad
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/common/acpi/upep.asl
1 file changed, 28 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/58274/3
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58282 )
Change subject: mb/google/guybrush: Disable HAVE_ACPI_RESUME / S3
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58282/comment/f8943189_8d308455
PS1, Line 9: S3 is not currently functional on Guybrush.
What does that mean exactly? Where does it fail?
Please give more background why this is not functional. AGESA?
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Change subject: mb/google/guybrush: Disable HAVE_ACPI_RESUME / S3
......................................................................
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58118 )
Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS8:
> > I think it makes sense to set it where the table is set. Also, the three-liner
> > repeated in soc/intel/*, I guess that belongs in cpu/intel/common/?
>
> You probably mean `cpu_get_cppc_table`? SKL will use common ACPI soon (CB:44138), so duplication will vanish.
>
Actually, the code calling cpu_get_cppc_table(). It seems odd to have parts of
generic code in soc/ and other parts in cpu/.
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Change subject: soc/amd/common/acpi/upep: Add Low Power State Entry Notifications
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/acpi/upep.asl:
https://review.coreboot.org/c/coreboot/+/58274/comment/2e6ec33b_8f1d454a
PS2, Line 11: ENTRY
> I can replace S0IX with "LOW_POWER" to match exactly in the document.
+1
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